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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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FPGA implementation of Object Recognition Processor for HDTV Resolution Video Using Sparse FIND Feature

FPGA Implementation of Object Recognition Processor for HDTV...

引用

ieee International workshop on signal processing systems (sips)

作者： Nishizumi, Yuri Matsukawa, Go Kajihara, Koichi Kodama, Taisuke Izumi, Shintaro Kawaguchi, Hiroshi Nakanishi, Chikako Goto, Toshio Kato, Takeo Yoshimoto, Masahiko Kobe Univ Grad Sch Syst Informat Kobe Hyogo 6578501 Japan Osaka Inst Technol Osaka 5358585 Japan Toyota Motor Co Ltd Elect Adv Dev Dept Toyota 4718571 Japan Toyota Cent Res & Dev Labs Inc Nagakute Aichi 4801192 Japan

ISBN: (纸本)9781538604465

This paper describes FPGA implementation of object recognition processor for HDTV resolution 30 fps video using the Sparse FIND feature. Two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction are proposed to perform a real time object recognition with enormous computational complexity. From implementation of the proposed architecture in the FPGA, it was confirmed that detection using the Sparse FIND feature was performed for HDTV images at 47.63 fps, on average, at 90 MHz. The recognition accuracy degradation from the original Sparse FIND-base object detection algorithm implemented on software was 0.5%, which shows that the FPGA system provides sufficient accuracy for practical use.

关键词： FPGA Sparse FIND HDTV resolution

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A switched current based FPAA macrocell for mixed mode signal processing systems

A switched current based FPAA macrocell for mixed mode signa...

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Halima, Moez Ben Fakhfakh, Mourad Loulou, Mourad Laboratoire d'Electronique et des Technologies de l'Information National Engineering School of Sfax Sfax Tunisia

ISBN: (纸本)0780393341

In this paper we present a switched current based macrocell block dedicated for field programmable analogue arrays. The macrocell uses a combination of class A switched current cells performing programmable basic analogue signal processing multifunction. In fact, by means of a set of static switches it allows us to configure basic linear discrete time functions such as lossless and damped integrators and differentiators. The proposed macrocell gets profit from the flexibility of switched current techniques implementing programmable filters, oscillators, control systems, and both ADC and DAC blocks. The present work highlights the main idea and a validation of the planned functions. Simulation results are presented showing the functionality of some examples. © 2005 ieee.

关键词： Switching systems

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Efficient Scalable Hardware Architecture for Highly Performant Encoded Neural Networks

Efficient Scalable Hardware Architecture for Highly Performa...

引用

ieee International workshop on signal processing systems (sips)

作者： Wouafo, Hugues Chavet, Cyrille Coussy, Philippe Danilo, Robin Univ Bretagne Sud Lab STICC Lorient France

ISBN: (纸本)9781538604465

Different neural network models have been proposed to design efficient associative memories like Hopfield networks, Boltzmann machines or Cogent confabulation. Compared to the classical models, Encoded Neural Network (ENN) is a recently introduced formalism with a proven higher efficiency. This model has been improved through different contributions like Clone-based ENN (CbNNs) or Sparse ENNs (S-ENNs) which enhance either the capacity of the original ENN or its retrieving performances. However, only very few works explored its hardware implementation for embedded applications. In this paper, we introduce a clone-based sparse neural network model (SC-ENN), that gathers the enhancements of the existing approaches in a single formal model. In addition, we present a dedicated scalable hardware architecture to implement SC-ENN. This work leads to significant complexity and area reduction without affecting neither memorizing nor retrieving performances. By only handling the most relevant information provided by the model, our proposed approach is far less expensive compared to state of the art solutions.

关键词： Neural network Hardware design FPGA

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High performance seed processors

High performance seed processors

引用

ieee workshop on signal processing systems

作者： Choi, HM Cho, HH Lee, SK Choi, MR Hanyang Univ Dept EECI ASIC Lab Seoul 133791 South Korea

ISBN: (纸本)0780377958

Currently, information security is an important issue in our information society and technology. In this paper, we propose two efficient architectures for processor of 128-bit block cipher SEED using 32-bit data bus. We compare the proposed architectures with the conventional SEED processor. The proposed SEED processors improve speed and reduce the hardware resources using only one G-function in the F-function and the key scheduler of SEED. The operation of the proposed methods has been verified with functional simulation, synthesis and tested on board. The proposed architecture is suited for hardware-critical applications, such as smart card, PDA, and mobile phone, etc.

关键词： Application specific integrated circuits Computer crime Cryptography Data security Field programmable gate arrays Hardware Process design Real time systems Software algorithms Throughput

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FPGA implementation of Kalman low-pass filter for applications in Sigma-Delta (Σ-Δ) demodulation

FPGA implementation of Kalman low-pass filter for applicatio...

引用

ieee workshop on signal processing systems

作者： Charoensak, C Abeysekera, SS Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

ISBN: (纸本)0780377958

Over the last few decades, the use of Sigma-Delta (Sigma-Delta) modulators, has moved into mainstream applications in signal processing such as A/D, D/A, and communication. Sigma-Delta modulators produce a single, or few bits output making them suitable for realization in VLSI circuits. For improved signal-to-quantization-noise ratio, higher order modulators, such as multi-loop and multi-stage architecture, are commonly used. The quantization noise behavior of these higher order modulators is well understood. Based on these quantization noise characteristics, various demodulator architectures, such as optimal FIR filter, Sinc filter, and Laguerre filter are reported in the literature. In this paper, an efficient FPGA (Field Programmable Gate Array) implementation of a Kalman recursive low-pass filter suitable for application in Sigma-Delta demodulation is reported. FPGA Synthesis results, as well as filter performance, as compared to previous designs for Sinc filter and Laguerre filter, is given.

关键词： Circuit noise Delta-sigma modulation Demodulation Field programmable gate arrays Finite impulse response filter Kalman filters Low pass filters Quantization signal processing Very large scale integration

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Audio application implementations on a block-floating-point DSP 16

Audio application implementations on a block-floating-point ...

引用

ieee workshop on signal processing systems (sips 02)

作者： Kobayashi, S Lee, SY Kino, T Kozuka, L Tokui, T Asahi Kasei Corporation Central Technology Laboratory Japan Asahi Kasei Microsystems Marketing and Sales Center Japan

ISBN: (纸本)0780375874

Hierarchical block-floating-point arithmetic (H-BFP) is applied to a configurable DSP architecture. This new arithmetic has been proposed in order to solve a trade-off problem between complexity and accuracy in implementing conventional block-floating-point arithmetics. This paper describes an actual implementation of the DSP architecture on a field programmable gate array (FPGA) platform. Some signal processing quality evaluation results are also presented for two audio applications that are realized on the DSP architecture.

关键词： Array signal processing Costs Digital signal processing Field programmable gate arrays Fixed-point arithmetic Floating-point arithmetic Hardware Laboratories Mobile communication signal processing

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Full Dimension MIMO (FD-MIMO) - Reduced complexity system design and real-time implementation

Full Dimension MIMO (FD-MIMO) - Reduced complexity system de...

引用

ieee International workshop on signal processing systems (sips)

作者： Xu, Gary Li, Yang Rajagopal, Sridhar Monroe, Robert Yuan, Jin Ramakrishna, Sudhir Nam, Young Han Zhang, Jianzhong (Charlie) Samsung Res Amer Dallas Stand & Mobil Innovat Lab Richardson TX 75080 USA

ISBN: (纸本)9781509033614

Full-Dimension MIMO (FD-MIMO) technology has been shown to increase spectral efficiency 2-4X compared to current LTE systems by exploiting a large number of antennas to support high order multiuser MIMO. High order multiuser MIMO with large number of antennas increase design and implementation complexity significantly. Furthermore, practical challenges such as antenna calibration for RF mismatches and failure need to be considered. In this paper, reduced-complexity precoding algorithm is introduced and optimized for real-time FPGA based implementation. Novel antenna calibration architecture is designed for FD-MIMO large 2-dimension array with the consideration of RF failure in practice. Field experimental results are also presented based on a proof of concept (PoC) FD-MIMO base-station (BS) with 32 antennas that supports up to 12 users and achieves spectral efficiency of similar to 21 bits/sec/Hz.

关键词： massive MIMO FD-MIMO precoding complexity reduction real-time

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Reliable fixed-point implementation of linear data-flows

Reliable fixed-point implementation of linear data-flows

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ieee International workshop on signal processing systems (sips)

作者： Hilaire, Thibault Volkova, Anastasia Ravoson, Maminionja UPMC Univ Paris 06 Sorbonne Univ UMR 7606 LIP6 F-75005 Paris France

ISBN: (纸本)9781509033614

In this article, we propose a complete methodology to implement a signal processing or control-engineering algorithm described with a linear data-flow into numerical code using fixed-point arithmetic. Our approach is based on a reliable determination of the Worst-Case Peak gain of a filter as well as on rigorous error analysis of roundoff error propagation. It guarantees that no overflow will occur and that the output error due to the finite precision implementation is less than a given bound. Without loss of generality, we consider the linear data-flows given in the form of Simulink block diagram. It is first transposed into an internal matrix-based representation and then the reliable evaluation of the magnitudes of each internal variable is performed. Our approach allows determining the minimum word-length required to achieve a given accuracy. Finally, the methodology is illustrated with numerical examples.

关键词： Fixed point arithmetic

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Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors

Efficient Emulation of Floating-Point Arithmetic on Fixed-Po...

引用

ieee International workshop on signal processing systems (sips)

作者： Gerlach, Lukas Paya-Vaya, Guillermo Blume, Holger Leibniz Univ Hannover Inst Microelect Syst Cluster Excellence Hearing4all Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9781509033614

In this paper, a software floating-point emulation library for fixed-point SIMD processors is proposed. The single instruction multiple data (SIMD) mechanism of those processors is exploited in this work to efficiently emulate fast software floating-point operations. The key feature of this approach is the independent processing of the significand and the exponent, stored in different sized subwords of one SIMD word. Additional processing performance is obtained by computing multiple floating-point operations in parallel using one SIMD instruction. Compared to related work, no additional hardware overhead is required to speed up the software emulation of floating-point arithmetic. An evaluation of fixed-and floatingpoint signal processing algorithms, implemented on a fixed-point VLIW-SIMD processor, shows the differences in performance, precision, and code size.

关键词： signal processing

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Efficient Bit-Channel Reliability Computation for Multi-Mode Polar Code Encoders and Decoders

Efficient Bit-Channel Reliability Computation for Multi-Mode...

引用

ieee International workshop on signal processing systems (sips)

作者： Condo, Carlo Hashemi, Seyyed Ali Gross, Warren J. McGill Univ Dept Elect & Comp Engn Montreal PQ Canada

ISBN: (纸本)9781538604465

Polar codes are a family of capacity-achieving error-correcting codes, and they have been selected as part of the next generation wireless communication standard. Each polar code bit-channel is assigned a reliability value, used to determine which bits transmit information and which parity. Relative reliabilities need to be known by both encoders and decoders: in case of multi-mode systems, where multiple code lengths and code rates are supported, the storage of relative reliabilities can lead to high implementation complexity. In this work, we observe patterns among code reliabilities, and propose an approximate computation technique to easily represent the reliabilities of multiple codes, through a limited set of variables and update rules. The proposed method allows to tune the trade-off between reliability accuracy and implementation complexity. An approximate computation architecture for encoders and decoders is designed and implemented, showing 50.7 % less area occupation than storage-based solutions, with less than 0.05 dB error correction performance degradation. Used within a standard SCL decoder, the proposed architecture results in up to 17.0 % less area occupation.

关键词： Decoding signal to noise ratio Encoding Complexity theory Reliability theory Computer architecture

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