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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

共 1150 条记录，以下是151-160 订阅

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design AND implementation OF A HIGH THROUGHPUT SOFT OUTPUT MIMO DETECTOR

DESIGN AND IMPLEMENTATION OF A HIGH THROUGHPUT SOFT OUTPUT M...

引用

ieee workshop on signal processing systems (sips)

作者： Hwang, Yin-Tsung Chen, Yi-Yo Natl Chung Hsing Univ Taichung 40227 Taiwan

ISBN: (纸本)9781467362382

In this paper, a new soft output MIMO decoder based on the k-best search scheme and additional partial Euclidian distance (PED) update schemes is developed. The k-best framework facilitates a constant throughput implementation and the PED update schemes help achieve a more accurate log-likelihood ratio (LLR) calculation. A LLR clamping technique is further adopted to enhance the BER performance when combining with the LDPC coding. Simulation results indicate the effectiveness of the proposed PED update schemes against previous works. Efficient architecture design is next developed capable of accomplishing one 4X4 MIMO signal vector detection every 4 clock cycles. In FPGA implementation, the maximum working frequency can be up to 121.3MHz and suggests a 720Mbps data rate for a 4X4 MIMO system using 64QAM modulation.

关键词： MIMO signal detector soft output FPGA k-best search

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EFFICIENT HARDWARE ARCHITECTURE FOR LARGE DISPARITY RANGE STEREO MATCHING BASED ON BELIEF PROPAGATION

EFFICIENT HARDWARE ARCHITECTURE FOR LARGE DISPARITY RANGE ST...

引用

ieee International workshop on signal processing systems (sips)

作者： Wu, Sih-Sian Tsai, Chen-Han Chen, Bang-Gee Natl Taipei Univ DSP IC Design Lab New Taipei 23741 Taiwan

ISBN: (纸本)9781509033614

This paper introduces an efficient hardware architecture for the belief propagation(BP) algorithm especially for large disparity range stereo matching applications. BP is a popular global optimization algorithm for labelling problems which is hardware friendly. There are few researches focus on BP implementation in large disparity range stereo matching problems, since traditional belief propagation hardware implementations suffer from a server trade-off between hardware efficiency and short critical path while the disparity range is larger than 64. In this paper, we eliminate the redundancy of previous BP implementation and propose an efficient architecture without introducing any delay overhead which is more suitable for large disparity range cases. As a result, the hardware complexity is reduced from O(L-2) to O(Llog(2) L), where L is the disparity range. We use a time-area term to demonstrate the trade-off between various architectures, results show that the proposed one can reach 49.6% and 71.2% reduction compared to the state-of-the-art implementation[1] with disparity ranges 64 and 128 respectively.

关键词： BP-M tile-based BP Hardware implementation stereo matching disparity estimation

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Non-sequential processing: bridging the semantic gap left by the von Neumann architecture.

Non-sequential processing: bridging the semantic gap left by...

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Verhulst, E Eonic Systems Inc

ISBN: (纸本)0780338065

Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be described to demonstrate how to overcome this gap. A more radical solution will then be described which no longer defines programming as a procedure that operates on data, but as a specification of data sets that require transformations. While this can be emulated on top of the CSP model, more efficient hardware implementations are possible. The author speculates that this could result in architectures that are hard real-time and optimised by design.

关键词： Parallel processing systems

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Energy/power estimation for LDPC decoders in software radio systems

Energy/power estimation for LDPC decoders in software radio ...

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Lee, Chia-Han Wolf, Wayne EE Department Princeton University

ISBN: (纸本)0780393341

Low-density parity-check (LDPC) codes are advanced error-correcting codes with performance approaching the Shannon limit. Although many LDPC code decoding algorithms have been proposed, no detailed comparison in energy/power consumption had ever been reported. This paper presents the performance and energy/power consumption trade-off for different LDPC decoding algorithms and proposes an efficient method to estimate energy consumption. We also propose a joint power management scheme for transmitter and receiver to save receiver energy while maintaining same communication quality by properly delivering more transmit power. © 2005 ieee.

关键词： Radio systems

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Index-based RNS DWT architectures for custom IC designs

Index-based RNS DWT architectures for custom IC designs

引用

ieee workshop on signal processing, systems design and implementation (sips 01)

作者： Ramírez, J Fernández, PG Meyer-Bäse, U Taylor, F Garcia, A Lloris, A Univ Granada Dept Elect & Tecnol Comp E-18071 Granada Spain

ISBN: (纸本)0780371453

The design of high-performance, high-precision, real-time digital signal processing (DSP) systems, such as those associated with wavelet signal processing, Is a challenging problem. This paper reports on the innovative use of the residue number system (RNS) for implementing high-end wavelet filter banks. The disclosed system uses an enhanced index-transformation defined over Galois fields to efficiently support different wavelet filter instantiations without adding any extra cost or additional lookup tables (LUT). An exhaustive comparison against existing two's complement (2C) designs for different custom IC technologies was carried out. These structures demonstrated to be well suited for field programmable logic (FPL) assimilation as well as for CBIC (cell-based integrated circuit) technologies.

关键词： Digital signal processing

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AUTOMATED GATEWARE DISCOVERY USING OPEN FIRMWARE

AUTOMATED GATEWARE DISCOVERY USING OPEN FIRMWARE

引用

ieee workshop on signal processing systems (sips)

作者： Rajan, Shanly Inggs, Michael Welz, Marc Univ Cape Town Dept Elect Engn ZA-7701 Rondebosch South Africa Square Kilometer Array South Africa ZA-7405 Cape Town South Africa

ISBN: (纸本)9781467362382

This paper presents the design and implementation of an automated gateware(1) discovery mechanism using generic reconfigurable computing hardware and toolflows. This mechanism was devised in an effort to build a software system with the goal to improve performance and reduce software development time spent on operating gateware pieces. It accomplishes this by reusing existing device drivers in the framework of the chosen technology, namely OF (Open Firmware).

关键词： signal processing field programmable gate arrays device drivers radio astronomy

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CRN-Based design Methodology for Synchronous Sequential Logic

CRN-Based Design Methodology for Synchronous Sequential Logi...

引用

ieee International workshop on signal processing systems (sips)

作者： Zhong, Zhiwei Ge, Lulu Shen, Ziyuan You, Xiaohu Zhang, Chuan Southeast Univ Lab Efficient Architectures Digital Commun & Sign Nanjing Jiangsu Peoples R China Southeast Univ Natl Mobile Commun Res Lab Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781538604465

With the aid of a storage-release mechanism named key-keysmith, an implementation approach based on chemical reaction networks (CRNs) for synchronous sequential logic is proposed. This design approach, which stores logic information in keysmith and releases it through key, primarily focuses on the underlying state transitions behind the required logic rather than the electronic circuit representation. Therefore, it can be uniformly and easily employed to implement any synchronous sequential logic with molecular reactions. Theoretical analysis and numerical simulations have demonstrated the robustness and universality of the proposed approach.

关键词： Molecule computing chemical reaction networks (CRNs) synchronous sequential logic state diagram (SD)

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Rich Representation Spaces: Benefits in Digital Auscultation signal Analysis

Rich Representation Spaces: Benefits in Digital Auscultation...

引用

ieee International workshop on signal processing systems (sips)

作者： Emmanouilidou, Dimitra Elhilali, Mounya Johns Hopkins Univ Elect & Comp Engn Dept Baltimore MD 21218 USA

ISBN: (纸本)9781509033614

When developing automated techniques for analysis of auscultation signals, the choice of a proper representational space that characterizes all attributes of interest in the signal is of paramount importance. In this paper, we investigate different feature representation methods and their benefits in distinguishing auscultation sounds. The importance of choosing an appropriate feature space is explored and validated using trained classifiers that distinguish between normal and abnormal respiratory sounds. Findings of this study are two-fold: i) an increased dimensionality in the feature space can provide a more complete and distinct representation of the delicate breath sounds and ii) dimensionality of the feature space alone is not enough to fully capture discriminative attributes: an informative feature space is even more crucial for extracting accurate, disease-specific characteristics of respiratory sounds.

关键词： biomedical signal processing digital auscultation lung sounds respiratory sounds computerized analysis multiresolution representation spectrotemporal analysis time-frequency analysis space analysis

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Cordic vector interpolator for power-aware 3D computer graphics 16

Cordic vector interpolator for power-aware 3D computer graph...

引用

ieee workshop on signal processing systems (sips 02)

作者： Euh, J Chittamuru, J Burleson, W Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)0780375874

Real-time 3D graphics will be a major power consumer in future portable embedded systems. In this paper we present a 3D CORDIC vector interpolator for power-aware graphics system. This new interpolator supports dynamic control of computing precision with an output accuracy range of 6 to 10 bits. The output precision control of this interpolator exploits the Human Visual Perception (HVP) to mask the image quality degradation resulting from low precision computation. The results of implementation and simulation show a 77% energy savings over a non-adaptive system while sharing no noticeable image quality degradation.

关键词： Computer architecture Computer graphics Degradation Energy consumption Hardware Humans Image quality Interpolation signal processing algorithms Visual perception

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A Channel-Adaptive Nonbinary LDPC Decoder

A Channel-Adaptive Nonbinary LDPC Decoder

引用

ieee International workshop on signal processing systems (sips)

作者： Huang, Wenjie Wang, Lei Univ Connecticut Dept Elect & Comp Engn Storrs CT 06269 USA

ISBN: (纸本)9781467396042

In this paper, we propose a low-complexity decoding message truncation technique for nonbinary LDPC decoders by exploiting the extended min-sum algorithm. The proposed technique dynamically adjusts the decoding message length according to channel conditions, thereby reducing the decoding complexity while conforming to the desired level of decoding performance. Utilizing the proposed technique, the decoding operations as well as the power consumption of the non-binary LDPC decoder can be greatly reduced. Simulation results demonstrate that the proposed technique can achieve a better power-performance tradeoff over conventional techniques.

关键词： NB-LDPC decoder Galois Field Extended Min-Sum Channel-aptive message control Low-complexity/low power design

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