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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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design and implementation of a complex multiplier using distributed arithmetic

Design and implementation of a complex multiplier using dist...

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Karlsson, M Vesterbacka, M Wanhammar, L Linkoping Univ Linkoping Sweden

ISBN: (纸本)0780338065

In this paper we propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b, and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting implementation of the complex multiplier has a maximum clock frequency of 250 MHz, consumes 70 mW, and occupies a chip area of 0.5 mm(2) in a double-metal 0.8 mu m process. The coefficient word length and the data word length are 12 bits and 16 bits, respectively.

关键词： signal processing

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Deep Neural Networks Characterization Framework for Efficient implementation on Embedded systems 34

Deep Neural Networks Characterization Framework for Efficien...

引用

34th ieee workshop on signal processing systems (sips)

作者： Ali, Nermine Philippe, Jean-Marc Tain, Benoit Peyret, Thomas Coussy, Philippe CEA LIST F-91191 Gif Sur Yvette France Univ South Brittany Lorient France

ISBN: (纸本)9781728180991

Bio-inspired machine learning algorithms, such as Convolutional Neural Networks (CNNs), offer interesting solutions to complex real-life problems that cannot be simply modeled. Applications involving image recognition and object detection can greatly benefit from these approaches. Furthermore, their intrinsic and regular parallel structure offer opportunities regarding hardware acceleration. However, moving compute and memory-intensive CNNs to embedded systems while maintaining high energy-efficiency remains challenging. This paper presents the first step of a generic framework targeting the characterization of neural network algorithms to improve their implementation on embedded systems. The presented approach aims at reducing the gap between the fast-changing landscape of applications based on artificial intelligence and the hardware targets. The framework computes different metrics from neural network descriptions (such as computation and memory needs or data locality and reuse) to derive appropriate implementation strategies, or configurations of target architectures. Based on the outputs of the framework, new neural networks topologies can be quickly studied to reduce time-to-market of new systems.

关键词： Convolutional Neural Networks design Space Exploration Embedded systems

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implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node 34

Implementation of a High-Throughput Fast-SSC Polar Decoder w...

引用

34th ieee workshop on signal processing systems (sips)

作者： Zheng, Haotian Balatsoukas-Stimming, Alexios Cao, Zizheng Koonen, Ton Eindhoven Univ Technol Dept Elect Engn NL-5612 AZ Eindhoven Netherlands

ISBN: (纸本)9781728180991

Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1/2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.

关键词： Decoding

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Quality-aware memory controller for multimedia platform SOC

Quality-aware memory controller for multimedia platform SOC

引用

ieee workshop on signal processing systems

作者： Lin, TC Lee, KB Jen, CW Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)0780377958

The ongoing advancements in VLSI technology allow SoC design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient memory controller that contains a quality-aware scheduler and a configurable DRAM memory interface socket to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Simulation results show that the latency of the latency-sensitive data flow can be reduced to 50%, and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.

关键词： Bandwidth Communication system control Control systems Costs Delay design engineering Processor scheduling Quality of service Random access memory System-on-a-chip

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A novel multipath matrix algorithm for exact room response identification in stereo echo cancellation

A novel multipath matrix algorithm for exact room response i...

引用

ieee workshop on signal processing systems

作者： Lai, JT Wu, AY Yeh, CC Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taiwan

ISBN: (纸本)0780377958

Stereo Echo Cancellation is the key technique to solve the echo problem in modern teleconference systems. There is fundamental problem in stereo echo cancellation - the misalignment between the converged filter weights and the real room impulse responses. Most of existing works explain the misalignment problem by a conceptual stochastic equation, and no studies have investigated the closed-form of the final weights in stereo echo canceller. In this paper, we formulate a governing equation, Multipath Matrix Equation (MME) to provide a systematic mathematic approach for the stereo echo cancellation system. Several phenomena of stereo NLMS algorithm can be explained by using above equation. Furthermore, we propose a new cancellation algorithm - Multipath Matrix Algorithm (MMA). It keeps the simplicity of Normalized Least Mean Square (NLMS) and can find out the real room impulse responses to exhibit better performance.

关键词： Acoustic applications Adaptive filters Algorithm design and analysis Audio systems Echo cancellers Equations Microphones Speech Stochastic processes Teleconferencing

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Low-Latency Software LDPC Decoders for x86 Multi-core Devices

Low-Latency Software LDPC Decoders for x86 Multi-core Device...

引用

ieee International workshop on signal processing systems (sips)

作者： Le Gal, Bertrand Jego, Christophe Univ Bordeaux IMS Lab Bordeaux INP Bordeaux France

ISBN: (纸本)9781538604465

LDPC codes are a family of error correcting codes used in most modern digital communication standards even in future 3GPP 5G standard. Thanks to their high processing power and their parallelization capabilities, prevailing multi-core and many-core devices facilitate real-time implementations of digital communication systems, which were previously implemented on dedicated hardware targets. Through massive frame decoding parallelization, current LDPC decoders throughputs range from hundreds of Mbps up to Gbps. However, inter-frame parallelization involves latency penalties, while in future 5G wireless communication systems, the latency should be reduced as far as possible. To this end, a novel LDPC parallelization approach for LDPC decoding on a multi-core processor device is proposed in this article. It reduces the processing latency down to some microseconds as highlighted by x86 multi-core experimentations.

关键词： Decoding Parity check codes Throughput Standards Program processors Parallel processing

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EM-based channel estimation for space time block coded MIMO OFDM systems

EM-based channel estimation for space time block coded MIMO ...

引用

ieee workshop on signal processing systems design and implementation

作者： Karkhanechi, Haideh M. Levy, Bernard C. Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)9781424403820

We propose a channel estimation technique based on an expectation maximization (EM) algorithm, for space-time block coded (STBC) multi-input njuldoutput (MIMO) OFDM systems. The channel estimation is done by decomposing the superimposed received signals, into their signal components and estimating the channelparameters of each signal component separately.

关键词： Channel estimation

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Advanced Wireless Digital Baseband signal processing Beyond 100 Gbit/s

Advanced Wireless Digital Baseband Signal Processing Beyond ...

引用

ieee International workshop on signal processing systems (sips)

作者： Weithoffer, Stefan Herrmann, Matthias Kestel, Claus Wehn, Norbert Univ Kaiserslautern Microelect Syst Design Res Grp D-67663 Kaiserslautern Germany

ISBN: (纸本)9781538604465

The continuing trend towards higher data rates in wireless communication systems will, in addition to a higher spectral efficiency and lowest signal processing latencies, lead to throughput requirements for the digital baseband signal processing beyond 100Gbit/s, which is at least one order of magnitude higher than the tens of Gbit/s targeted in the 5G standardization. At the same time, advances in silicon technology due to shrinking feature sizes and increased performance parameters alone won't provide the necessary gain, especially in energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. In this paper, we highlight the challenges for wireless digital baseband signal processing beyond 100Gbit/s and the limitations of today's architectures. Our focus lies on the channel decoding and MIMO detection, which are major sources of complexity in digital baseband signal processing. We discuss techniques on algorithmic and architectural level, which aim to close this gap. For the first time we show Turbo-Code decoding techniques towards 100Gbit/s and a complete MIMO receiver beyond 100Gbit/s in 28 nm technology.

关键词： Decoding Throughput Turbo codes Iterative decoding Mobile communication Baseband

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PARAMETERIZED CORE FUNCTIONAL DATAFLOW GRAPHS AND THEIR APPLICATION TO design AND implementation OF WIRELESS COMMUNICATION systems

PARAMETERIZED CORE FUNCTIONAL DATAFLOW GRAPHS AND THEIR APPL...

引用

ieee workshop on signal processing systems (sips)

作者： Wang, Lai-Huei Shen, Chung-Ching Bhattacharyya, Shuvra S. Univ Maryland College Pk MD 20742 USA

ISBN: (纸本)9781467362382

Due to the increased complexity of dynamics in modern DSP applications, dataflow-based design methodologies require significant enhancements in modeling and scheduling techniques to provide for efficient and flexible handling of dynamic behavior. In this paper, we address this problem through a new framework that is based on integrating two complementary modeling techniques, core functional dataflow (CFDF) and parameterized synchronous dataflow (PSDF). We apply, in a systematically integrated way, the structured mode-based dynamic dataflow modeling capability of CFDF together with the features of PSDF for dynamic parameter reconfiguration and quasi-static scheduling. We refer to this integrated methodology for mode-and dynamic-parameter-based modeling and scheduling as core functional parameterized synchronous dataflow (CF-PSDF). Through a wireless communication case study involving MIMO detection, we demonstrate the utility of design and implementation using CF-PSDF graphs. Experimental results on this case study demonstrate the efficiency and flexibility of our proposed new CF-PSDF based design methodology.

关键词： Dataflow graph parameterized modeling dynamic scheduling MIMO detector

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Reconfigurable discrete wavelet transform architecture for advanced multimedia systems

Reconfigurable discrete wavelet transform architecture for a...

引用

ieee workshop on signal processing systems

作者： Tseng, PC Huang, CT Chen, LG Natl Taiwan Univ Grad Inst Elect Engn DSP IC Design Lab Taipei 10764 Taiwan

ISBN: (纸本)0780377958

In this paper, a novel reconfigurable discrete wavelet transform architecture is proposed to meet the diverse computing requirements of advanced multimedia systems. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35mum 1P4M CMOS process, and at 50MHz, it can achieve at most 100M pixel/sec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced multimedia systems.

关键词： Computational efficiency Computer architecture design methodology Discrete wavelet transforms Filters Hardware Kernel Multimedia systems Prototypes Runtime

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