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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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Algorithm and architecture of video segmentation hardware system with a programmable PE array 16

Algorithm and architecture of video segmentation hardware sy...

引用

ieee workshop on signal processing systems (sips 02)

作者： Chien, SK Huang, W Hsieh, BY Chen, LG Natl Taiwan Univ Grad Inst Elect Engn DSP IC Design Lab Taipei 106 Taiwan

ISBN: (纸本)0780375874

Video segmentation is a key unit in content-based video encoding systems, such as MPEG-4. Existing algorithms are too complex for real-time applications, and hardware implementation is infeasible because of the global and irregular operations. In this paper, a hardware system for video segmentation is proposed from algorithm level to hardware architecture level. A hardware-oriented algorithm is first proposed to generate accurate object masks with local pixel operations and morphological operations, which are suitable for hardware implementation. After that, the hardware architecture is designed based on partial-result-reuse architecture and programmable morphology PE array architecture, which can achieve both high flexibility and throughput. A prototype chip is implemented to achieve the processing speed of 30 QCIF frames per second and 7,680 morphological operations per second at 26 MHz. It also shows the hardware cost is small, and the proposed video segmentation hardware system is suitable to be integrated into any content-based video encoding systems.

关键词： Algorithm design and analysis Change detection algorithms Encoding Hardware Image segmentation Morphological operations Morphology MPEG 4 Standard Real time systems Throughput

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FPGA implementation of an Efficient Adaptive Predistortion Algorithm

FPGA Implementation of an Efficient Adaptive Predistortion A...

引用

ieee International workshop on signal processing systems (sips)

作者： Cheng, Xin Zhu, Zhenghang Yao, Saijie Qian, Hua ShanghaiTech Univ Sch Informat Sci & Technol Shanghai Peoples R China Shanghai Res Ctr Wireless Commun Shanghai Peoples R China Chinese Acad Sci Shanghai Inst Microsyst & Informat Technol Shanghai Peoples R China

ISBN: (纸本)9781467396042

In modern wireless communication systems, the adaptive digital predistortion (DPD) is widely used to compensate for the nonlinearity in the radio front-end. In the DPD implementation, the conventional coefficient estimation algorithm is computationally intensive and prevents the application of complex DPD models. In [1], we have derived an efficient coefficients estimation algorithm based on orthonormal basis functions that achieves the low computational complexity while maintaining the estimation accuracy. In this paper, we focus on the implementation of this efficient coefficients estimation algorithm on a field programmable gate array (FPGA) platform. Compared with the conventional recursive least squares (RLS) algorithm, the low complexity algorithm can achieve the same linearization performance while saving about 80% hardware resources.

关键词： Power amplifier (PA) digital predistortion (DPD) recursive least squares (RLS) least mean squares (LMS)

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VLSI architecture design of rake receivers for cdma2000 systems 16

VLSI architecture design of rake receivers for cdma2000 syst...

引用

ieee workshop on signal processing systems (sips 02)

作者： Lee, S Kim, J Yonsei Univ Dept Elect & Elect Engn Seoul 120749 South Korea

ISBN: (纸本)0780375874

We propose low-complexity architecture for rake receivers in cdma2000 systems. The hardware cost of rake receivers is significantly increased in cdma2000 systems, because rake receivers should demodulate multi-path signals transmitted through multiple sub-carriers. We, therefore, present a novel architecture which adopts a multi-finger structure, arithmetic units shared by multi-fingers, and time-deskew buffers using a pre-combining technique. The results show that the proposed receiver reduces the hardware complexity by about 49.4% compared with a conventional one.

关键词： Arithmetic Costs Demodulation Fading Fingers Frequency estimation Hardware Multiaccess communication Multipath channels Very large scale integration

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Memory power reduction for the high-speed implementation of turbo codes

Memory power reduction for the high-speed implementation of ...

引用

ieee workshop on signal processing, systems design and implementation (sips 01)

作者： Maessen, F Giulietti, A Bougard, B Derudder, V Van der Perre, L Catthoor, F Engels, M IMEC Louvain Belgium

ISBN: (纸本)0780371453

Turbo codes achieve the highest coding gain known and should be the best candidates for error correction in high-speed wireless systems. However, the standard implementation of their decoding standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we systematically analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture. This optimization reduces the latency by a factor 600 and the energy per bit by a factor 20, allowing turbo codes application in future high-speed mobile systems.

关键词： Turbo codes

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A technique for reducing complexity of recursive motion estimation algorithms

A technique for reducing complexity of recursive motion esti...

引用

ieee workshop on signal processing systems

作者： Beric, A de Haan, G Sethuraman, R van Meerbergen, J Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)0780377958

The recursive search motion estimation algorithm offers smooth and accurate motion vector fields. Computationally, the most expensive part of the motion estimator is the evaluation of the various motion vector candidates. Evaluation is performed by comparing blocks in two consecutive frames pointed by motion vector candidates. This paper addresses the issue of reducing the already extremely low number of motion vector evaluations. We apply pre-processing techniques to reduce the number of motion vector candidates from 7 to 5, i.e. 30% without sacrificing quality. We exemplify the above findings through experimental results obtained using the 3-D recursive search motion estimation algorithm. The required pre-processing overhead is negligible.

关键词： Bandwidth Communication channels Electronic mail Image storage Laboratories Motion estimation Noise reduction Performance evaluation Real time systems TV

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HiBRID-SoC: A multi-core SoC architecture for multimedia signal processing

HiBRID-SoC: A multi-core SoC architecture for multimedia sig...

引用

ieee workshop on signal processing systems

作者： Stolberg, HJ Berekovic, M Friebe, L Moch, S Kulaczewski, MB Dehnhardt, A Pirsch, R Leibniz Univ Hannover Inst Mikroelektron Syst D-30167 Hannover Germany

ISBN: (纸本)0780377958

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range Of Multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 mum 6LM standard-cell technology, Occupies about 82 mm(2), and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full TV resolution requires about 120 MHz for real-time performance on the HiBRID-SoC, utilizing only two of the three cores.

关键词： Cost function Decoding High performance computing Image coding Image processing MPEG 4 Standard Multimedia systems signal processing System-on-a-chip Video signal processing

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Full chip false timing-path identification

Full chip false timing-path identification

引用

ieee Annual workshop on signal processing systems: design and implementation

作者： Zeng, J Abadir, M Bhadra, J Abraham, J Motorola Inc Somerset Design Ctr Austin TX 78729 USA

ISBN: (纸本)0780364880

Static timing analysis sets the industry standard in the design methodology to gage the speed of high performance microprocessors. Unfortunately, not all the paths identified using such analysis can be sensitized. This leads to a pessimistic estimation of processor speed, and the engineering efforts spent optimizing such paths can not improve the performance of the chip. In the past, we demonstrated initial results of how ATPG technique can be used to eliminate false paths efficiently[1]. Due to the gap between the physical design on which the static timing analysis of the chip is based and the test view on which ATPG technique is applied to eliminate false paths, in many cases only sections of some of the paths in the full-chip were analyzed in our initial results. In this paper, we will fully analyze all the timing paths using the ATPG technique overcoming the gap between the testing and timing analysis techniques. We applied our method on the second G4(1) PowerPC(TM).

关键词： Microprocessor chips

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Study of cache system in video signal processors

Study of cache system in video signal processors

引用

1998 ieee workshop on signal processing systems - design and implementation (sips'98)

作者： Wu, Z Wolf, W Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0780349970

Memory system design is especially important for video signal processing, where the video signal processor (VSP) not only requires a lot of data, but also needs a very high bandwidth and low latency. While caches become ubiquitous in modern systems, their performance still falls behind that of the processors. Therefore a number of modifications to traditional caches have emerged: victim cache, stream buffer, data prefetching techniques, et al. However, few people have studied cache memory for VSPs. In this paper, we present a case study based on extensive trace-driven scheduling, which shows that while stream buffer and stride prediction table are very effective for streaming video data, they should be applied in a different way in dedicated VSPs with higher degrees of parallelism than in current super-scalar workstation architectures.

关键词： VSP cache stream buffer stride prediction table trace-driven scheduling video applications VLIW

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An efficient high-speed block turbo code decoding algorithm and hardware architecture design

An efficient high-speed block turbo code decoding algorithm ...

引用

ieee workshop on signal processing systems

作者： Yoo, K Shin, H Jung, Y Lee, J Kim, A Yonsei Univ Seoul 120749 South Korea

ISBN: (纸本)0780377958

In this paper, we propose a high speed block turbo code decoding algorithm and design hardware architecture. Block turbo code(BTC)s support variable code rates and packet sizes and show a high-performance owing to a soft decision iteration decoding of turbo codes. However, BTCs have a long decoding time because of a iteration decoding and complicated extrinsic information operation. The proposed algorithm using the threshold that represents a channel information reduces the long decoding time. The threshold is decided by the absolute mean and the standard deviation of a LLR(Log Likelihood Ratio) in consideration that the LLR distribution is a Gaussian one. In the result of the logic synthesis using 0.35 mum CMOS technology, it is proved that the decoder applied by the propose algorithm reduce the decoding time by about 30% and include about 20K logic gates and 32Kbit memory sizes.

关键词： Algorithm design and analysis CMOS logic circuits Hardware Iterative algorithms Iterative decoding Multimedia communication Multimedia systems Testing Turbo codes Wireless communication

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A Robust Data-Driven Approach to the Decoding of Pyloric Neuron Activity

A Robust Data-Driven Approach to the Decoding of Pyloric Neu...

引用

ieee International workshop on signal processing systems (sips)

作者： dos Santos, Filipa Andras, P. Collins, D. J. Lam, K. P. Keele Univ Sch Comp & Math Newcastle Under Lyme England

ISBN: (纸本)9781538604465

The combination of intra and extra-cellular recording of small neuronal circuits such as stomatogastric nervous systems of the crab (Cancer borealis) is well documented and routinely practised. Voltage sensitive dye imaging (VSDi) is a promising technology for the simultaneous monitoring of neuronal activities in such a system. However, integrating data obtained from optical VSDi and electrophysiological recording of the lateral ventricular nerve (lvn) is a complex and exacting task. Our early work demonstrated some of the concepts and principle involved. In this paper, we examine and report on the results obtained from the application of signal processing techniques to three datasets for which we had VSDi and lvn data. Whilst significant challenges remain, we show that such an approach offers the possibility of real-time monitoring using automated analysis of VSDi data streams without the requirement for either extracellular (lvn) or intracellular recording.

关键词： multiresolution signal processing optical recording singular spectrum analysis stomatogastric ganglion pyloric rhytm voltage sensitive dye

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