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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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Contrastive Learning in Memristor-Based Neuromorphic systems

Contrastive Learning in Memristor-Based Neuromorphic Systems

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ieee workshop on signal processing systems (sips)

作者： Cory Merkel Alexander G. Ororbia Brain Lab Rochester Institute of Technology Rochester NY Neural Adaptive Computing Lab Rochester Institute of Technology Rochester NY

ISBN: (数字)9798350373752

ISBN: (纸本)9798350373769

Spiking neural networks have become an important family of neuron-based models that sidestep many of the key limitations facing modern-day backpropagation-trained deep networks, including their high energy inefficiency and long-criticized biological implausibility. In this work, we design and investigate a proof-of-concept instantiation of contrastive-signal-dependent plasticity (CSDP), a neuromorphic form of forward-forward-based, backpropagation-free learning. Our experimental simulations demonstrate that a hardware implementation of CSDP is capable of learning simple logic functions without the need to resort to complex gradient calculations.

关键词： Neuromorphics Biological system modeling Current measurement Neurons Contrastive learning Spiking neural networks signal processing Logic functions Hardware Synapses

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A Novel Blind Detection Method and FPGA implementation for Energy-Efficient Sidelink Communications

A Novel Blind Detection Method and FPGA Implementation for E...

引用

35th ieee workshop on signal processing systems (ieee sips)

作者： Zhang, Chenhao Hu, Haiqin Cao, Shan Jiang, Zhiyuan Shanghai Univ Sch Commun & Informat Engn Shanghai 200444 Peoples R China

ISBN: (纸本)9781665401449

A novel physical sidelink control channel (PSCCH) blind detection method based on demodulation reference signal (DMRS) detection is proposed for sidelink communications in cellular vehicular-to-everything (C-V2X). In the proposed method, the user equipment (UE) first performs coherent energy detection on the DMRS positions. According to the information of the time/frequency location where the DMRS is detected, the UE can adjust the decoding area to minimize unnecessary blind decoding attempts. Based on the proposed algorithm and the channel estimation method, a VLSI architecture of joint energy detection and channel estimation (JEC) is proposed. Reference implementation results for a Xilinx Virtex-7 FPGA show that our design can reduce hardware complexity and energy consumption.

关键词： LTE-V PSCCH DMRS VLSI energy efficiency

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design and implementation of a Highly Accurate Stochastic Spiking Neural Network

Design and Implementation of a Highly Accurate Stochastic Sp...

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35th ieee workshop on signal processing systems (ieee sips)

作者： Tang, Chengcheng Han, Jie Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

ISBN: (纸本)9781665401449

The emergence of spiking neural networks (SNNs) provide a promising approach to the energy efficient design of artificial neural networks (ANNs). The rate encoded computation in SNNs utilizes the number of spikes in a time window to encode the intensity of a signal, in a similar way to the information encoding in stochastic computing. Inspired by this similarity, this paper presents a hardware design of stochastic SNNs that attains a high accuracy. A design framework is elaborated for the input, hidden and output layers. This design takes advantage of a priority encoder to convert the spikes between layers of neurons into index-based signals and uses the cumulative distribution function of the signals for spike train generation. Thus, it mitigates the problem of a relatively low information density and reduces the usage of hardware resources in SNNs. This design is implemented in field programmable gate arrays (FPGAs) and its performance is evaluated on the MNIST image recognition dataset. Hardware costs are evaluated for different sizes of hidden layers in the stochastic SNNs and the recognition accuracy is obtained using different lengths of stochastic sequences. The results show that this stochastic SNN framework achieves a higher accuracy compared to other SNN designs and a comparable accuracy as their ANN counterparts. Hence, the proposed SNN design can be an effective alternative to achieving high accuracy in hardware constrained applications.

关键词： Field programmable gate arrays (FPGAs) priority encoder stochastic computing spiking neural networks

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Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators

Exploration and Generation of Efficient FPGA-based Deep Neur...

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35th ieee workshop on signal processing systems (ieee sips)

作者： Ali, Nermine Philippe, Jean-Marc Tain, Benoit Coussy, Philippe Univ Paris Saclay CEA List F-91120 Palaiseau France Univ South Brittany Lorient France

ISBN: (纸本)9781665401449

Convolutional Neural Networks (CNNs) have emerged as an answer to next-generation applications such as complex image recognition and object detection. Embedding such compute-intensive and memory-hungry algorithms on edge systems will lead to smarter high-value applications. However, the algorithmic innovations in the CNN field leave the hardware accelerators one step behind. Reconfigurable hardware (e.g. FPGAs) allows designing custom accelerators adapted to new algorithms. Furthermore, new design approaches such as high-level synthesis (HLS) enable to generate RTL code based on high-level function descriptions. This paper presents a high-level CNN accelerator generation framework for FPGAs. A first phase of the framework characterizes CNN descriptions using hardware-aware metrics. These metrics then drive a hardware generation phase which builds the proper C source code implementation for each layer of the network. Finally, an HLS tool outputs the synthesizable RTL code of the accelerator. This approach aims at reducing the gap between the evolving applications based on artificial intelligence and hardware accelerators, thus reducing time-to-market of new systems.

关键词： Convolutional Neural Networks design Space Exploration High Level Synthesis Embedded systems FPGA

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Proceedings - 2021 ieee workshop on signal processing systems, sips 2021

Proceedings - 2021 IEEE Workshop on Signal Processing System...

引用

2021 ieee workshop on signal processing systems, sips 2021

ISBN: (纸本)9781665401449

The proceedings contain 47 papers. The topics discussed include: understanding the energy vs. adversarial robustness trade-off in deep neural networks;design and implementation of autoencoder-LSTM accelerator for edge outlier detection;OneAI - novel multipurpose deep learning algorithms for UWB wireless networks;beam-slicing for jammer mitigation in mmWave massive MU-MIMO;a stage-wise conversion strategy for low-latency deformable spiking CNN;a novel blind detection method and FPGA implementation for energy-efficient sidelink communications;initial analysis of dynamic panel activation for large intelligent surfaces;and low-latency parallel Hermitian positive-definite matrix inversion for massive MIMO.

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A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm

A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Comp...

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ieee workshop on signal processing systems (sips)

作者： Tao Chen Suwen Song Zhongfeng Wang School of Electronic Science and Engineering Nanjing University Nanjing China School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (数字)9798350373752

ISBN: (纸本)9798350373769

This paper delves into recent hardware implementations of the Lempel-Ziv 4 (LZ4) algorithm, highlighting two key factors that limit the throughput of single-kernel compressors. Firstly, the actual parallelism exhibited in single-kernel designs falls short of the theoretical potential. Secondly, the clock frequency is constrained due to the presence of the feedback loops. To tackle these challenges, we propose a novel scheme that restricts each parallelization window to a single match, thus elevating the level of actual parallelism. Furthermore, by restricting the maximum match length, we eliminate the feedback loops within the architecture, enabling a significant boost in throughput. Finally, we present a high-speed hardware architecture. The implementation results demonstrate that the proposed architecture achieves a throughput of up to 16.10 Gb/s, exhibiting a 2.648× improvement over the start-of-the-art. The new design only results in an acceptable compression ratio reduction ranging from 4.93% to 11.68% with various numbers of hash table entries, compared to the LZ4 compression ratio achieved by official software implementations disclosed on GitHub.

关键词： Feedback loop Computer architecture Parallel processing signal processing Throughput Software Parallel architectures Compression algorithms Hardware acceleration Software development management

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Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communications: A Hardware Accelerator implementation for Reflection Optimization

Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communi...

引用

ieee workshop on signal processing systems (sips)

作者： Dimitris Kompostiotis Vassilis Paliouras Electrical and Computer Engineering Department University of Patras Greece

ISBN: (数字)9798350373752

ISBN: (纸本)9798350373769

Sixth generation (6G) wireless networks envision new Internet-of- Things (IoT) applications that require faster and more secure data transmission. Reconfigurable intelligent surfaces (RISs) can improve physical-layer security in wireless communications by optimally reflecting incoming electromagnetic waves to benefit legitimate users (LUs) and simultaneously hinder eavesdroppers (ED). However, for low-latency data transmission and short-coherence-time wireless channels, optimizing the RIS configuration must be done extremely fast, thus requiring a hardware accelerator. In this paper, we consider a multi-input multiple-output (MIMO) RIS-enabled physical-layer security system and introduce a novel low-latency hardware accelerator to maximize the achievable secrecy rate by optimizing the RIS reflection coefficients. The proposed accelerator implements a Dinkelbach-based iterative algorithm, here modified for the MIMO case and to facilitate hardware implementation. Simulations reveal that high-quality solutions are obtained, compared to a theoretical upper limit. The proposed sub-1-ms latency accelerator is detailed, highlighting design choices that enable its fast operation under moderate resource requirements, and also meeting the real-time requirements of emerging 6G applications.

关键词： 6G mobile communication Conferences Wireless networks Reconfigurable intelligent surfaces Real-time systems Reflection coefficient Security Data communication Low latency communication Hardware acceleration

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Box Decoding: A Low-Complexity Algorithm for MIMO Detection

Box Decoding: A Low-Complexity Algorithm for MIMO Detection

引用

ieee workshop on signal processing systems (sips)

作者： Sheikh Faizan Qureshi Stefan A. Damjancevic Emil Matus Dmitry Utyansky Pieter Van Der Wolf Gerhard P. Fettweis Vodafone Chair TU Dresden Dresden Germany Synopsys Inc. Sunnyvale USA Synopsys Inc. Eindhoven The Netherlands Barkhausen Institut CeTI TU Dresden Dresden Germany

ISBN: (数字)9798350373752

ISBN: (纸本)9798350373769

The selection of an algorithm for MIMO detection often involves a trade-off between detection performance and the efficiency of the implementation. Tree-based algorithms, such as Sphere Decoding (SD), offer superior performance compared to linear schemes like MMSE and ZF and non-linear schemes like successive interference cancellation (SIC). In the SD approach, the algorithm must select the most suitable branch at each tree node. Due to this conditional behavior, the number of computational steps is data-dependent and is only determined at run-time. Moreover, due to the sequential nature of the tree traversal, it is not well suited for parallel implementation on a modern vector DSP. Approaches like K-Best exist to address this challenge, but they remain computationally intense, especially for higher-order QAM modulations. We study the use case of the 5G-based IoT standard NR-Redcap, which requires a low-complexity baseband kernel implementation for a cost-effective modem design. We propose a novel MIMO detection scheme called Box Decoding, whose computational complexity does not depend on the QAM modulation order and offers a significant reduction in complexity compared to K - Best for our chosen use case. Furthermore, the algorithm doesn't necessitate the expensive sorting of candidate symbols, making it particularly appealing for implementation on contemporary vector Digital signal Processors (DSPs). Testing on a 64QAM modulation system for Redcap indicates negligible MIMO detection performance degradation compared to K-Best, with significantly lower complexity. For our use case, the Box Decoding algorithm proves to be a cost-effective implementation scheme for MIMO detection in 5G IoT modems, offering a 2dB SNR gain over MMSE-based SIC for an extra $23{\%}$ of clock cycles consumed for this task on a 512-bit vector DSP.

关键词： Interference cancellation Quadrature amplitude modulation signal processing algorithms Modulation Modems Vectors Decoding Kernel Standards Sorting

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implementation of a High-Throughput Fast-SSC Polar Decoder with Sequence Repetition Node 34

Implementation of a High-Throughput Fast-SSC Polar Decoder w...

引用

34th ieee workshop on signal processing systems (sips)

作者： Zheng, Haotian Balatsoukas-Stimming, Alexios Cao, Zizheng Koonen, Ton Eindhoven Univ Technol Dept Elect Engn NL-5612 AZ Eindhoven Netherlands

ISBN: (纸本)9781728180991

Even though polar codes were adopted in the latest 5G cellular standard, they still have the fundamental problem of high decoding latency. Aiming at solving this problem, a fast simplified successive cancellation (Fast-SSC) decoder based on the new class of sequence repetition (SR) nodes has been proposed recently in [1] and has a lower required number of time steps than other existing Fast-SSC decoders in theory. This paper focuses on the hardware implementation of this SR node-based fast-SSC (SRFSC) decoder. The implementation results for a polar code with length 1024 and code rate 1/2 show that our implementation has a throughput of 505 Mbps on an Altera Stratix IV FPGA, which is 17.9% higher with respect to the previous work.

关键词： Decoding

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Deep Neural Networks Characterization Framework for Efficient implementation on Embedded systems 34

Deep Neural Networks Characterization Framework for Efficien...

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34th ieee workshop on signal processing systems (sips)

作者： Ali, Nermine Philippe, Jean-Marc Tain, Benoit Peyret, Thomas Coussy, Philippe CEA LIST F-91191 Gif Sur Yvette France Univ South Brittany Lorient France

ISBN: (纸本)9781728180991

Bio-inspired machine learning algorithms, such as Convolutional Neural Networks (CNNs), offer interesting solutions to complex real-life problems that cannot be simply modeled. Applications involving image recognition and object detection can greatly benefit from these approaches. Furthermore, their intrinsic and regular parallel structure offer opportunities regarding hardware acceleration. However, moving compute and memory-intensive CNNs to embedded systems while maintaining high energy-efficiency remains challenging. This paper presents the first step of a generic framework targeting the characterization of neural network algorithms to improve their implementation on embedded systems. The presented approach aims at reducing the gap between the fast-changing landscape of applications based on artificial intelligence and the hardware targets. The framework computes different metrics from neural network descriptions (such as computation and memory needs or data locality and reuse) to derive appropriate implementation strategies, or configurations of target architectures. Based on the outputs of the framework, new neural networks topologies can be quickly studied to reduce time-to-market of new systems.

关键词： Convolutional Neural Networks design Space Exploration Embedded systems

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