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Efficient implementation of convolution and Winograd on ASMP embedded multicore vector processor 34

Efficient implementation of convolution and Winograd on ASMP...

引用

34th ieee workshop on signal processing systems (sips)

作者： Leclaire, Nicolas Mancini, Stephane Delnondedieu, Claude Henriques, Jean-Paul STMicroelectronics Grenoble France TIMA Lab Grenoble France

ISBN: (纸本)9781728180991

Efficient inference of Convolutional Neural Network (CNN) is a challenging task and design choices heavily rely on the target context and size of the CNN model. Many devices are available, each one targeting a specific class of application. The most famous ones target the server-side of cloud applications and some focus on embedded applications. In this paper we show how to exploit the low-level hardware features of an embedded multicore called STxP70 ASMP, each core being equipped with a vector coprocessor. This work shows how to adapt the algorithm to the platform and vice-versa, and provides an original algorithmic transform to optimize internal resources. Experiments are made to study the effect of numerous design parameters and CNN configurations. The results show the benefits of the proposed strategy and outline the low-level hardware features required to further optimize CNN inference.

关键词： convolution Winograd embedded multicore vector processor

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MEMS Inertial Motion Sensing Watch for Measuring Walking and Running Activities

MEMS Inertial Motion Sensing Watch for Measuring Walking and...

引用

ieee International workshop on signal processing systems (sips)

作者： Bardyn, F. Savary, M. Grassi, S. Farine, P-A. Fasel, B. Aminian, K. Ecole Polytech Fed Lausanne Elect & Signal Proc Lab CH-2002 Neuchatel Switzerland Ecole Polytech Fed Lausanne Lab Movement Anal & Measurement CH-1015 Lausanne Switzerland

ISBN: (纸本)9781509033614

This paper describes the development of a sport watch, as well as the software and hardware required to design an integrated solution for getting feedback during and after walking and running activities. The developed system is autonomous, so that neither a smartphone nor a computer are necessary for configuration. The user controls the watch via a touch-screen based interface and all the relevant information is displayed on an LCD. Moreover, the watch contains all the required inertial sensors to allow giving different feedbacks to the user, such as the type of activity, the number of steps taken, the covered distance, the instantaneous speed and the average speed. Although this work is multidisciplinary, in this paper the emphasis is put on the description of the device and on the electronics and the algorithms implementation. Particular focus is on the efficiency in terms of computational time, and in achieving high autonomy on a primary cell battery.

关键词： Inertial sensor accelerometer wrist watch pedometer step counter distance estimation speed estimation

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2001 ieee workshop on signal processing systems design and implementation

2001 IEEE Workshop on Signal Processing Systems Design and I...

引用

ieee workshop on signal processing systems- design and implementation-(sips) 2001

The proceedings contains 47 papers. Topics discusses include channel coding, signal processing algorithms, TV broadcast, scalable image and video processing, telecom design issues and video codecs.

关键词： signal processing

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VLSI architecture for discrete wavelet transform based on B-spline factorization

VLSI architecture for discrete wavelet transform based on B-...

引用

ieee workshop on signal processing systems

作者： Huang, CT Tseng, PC Chen, LG Natl Taiwan Univ Grad Inst Elect Engn DSP IC Design Lab Taipei 10764 Taiwan

ISBN: (纸本)0780377958

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of Pascal implementation. And the latter is the only part requiring multipliers and can be implemented with Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could need fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with small area and low speed adders because only few adders are on the critical path. Two cases of the JPEG2000 defaulted (9,7) filter and the (6,10) filter are given to demonstrate the efficiency of the proposed architectures.

关键词： Art Channel bank filters Chaos Convolution Digital signal processing Discrete wavelet transforms Filter bank Finite impulse response filter Spline Very large scale integration

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design of a lattice decoder for MIMO systems in FPGA

Design of a lattice decoder for MIMO systems in FPGA

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ieee workshop on signal processing systems design and implementation

作者： Ma, J Huang, XM Univ New Orleans Dept Elect Engn New Orleans LA 70148 USA

ISBN: (纸本)0780385047

Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of the MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.

关键词： lattice decoder closest point search MIMO FPGA

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PROGRAMMING GRAPHICS processing UNITS IN THE RVC-CAL DATAFLOW LANGUAGE

PROGRAMMING GRAPHICS PROCESSING UNITS IN THE RVC-CAL DATAFLO...

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ieee International workshop on signal processing systems (sips)

作者： Boutellier, J. Nylanden, T. Univ Oulu Dept Comp Sci & Engn Oulu Finland

ISBN: (纸本)9781467396042

The interest towards programming of streaming applications using dataflow models of computation has been increasing steadily in the recent years. Among the numerous dataflow formalisms, the ISO-standardized RVC-CAL dataflow language has offered a solid basis for programming tool development and research. To this date RVC-CAL programming tools have enabled transforming dataflow programs into concurrent executables for multicore processors, as well as for generating synthesizable hardware descriptions. In this paper it is shown how the RVC-CAL dataflow language can be used for programming graphics processing units (GPUs) with high efficiency. Considering the processing architectures of recent mobile and desktop computing devices, this advance is of high importance, as most consumer devices contain a graphics processing unit nowadays. To evaluate the proposed solution, the paper presents a video processing application case study. At best, the solution is shown to provide a speedup of 42x over single-threaded CPU execution.

关键词： Dataflow computing design automation parallel processing

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Models of Architecture: Reproducible Efficiency Evaluation for signal processing systems

Models of Architecture: Reproducible Efficiency Evaluation f...

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ieee International workshop on signal processing systems (sips)

作者： Pelcat, Maxime Desnos, Karol Maggiani, Luca Liu, Yanzhou Heulot, Julien Nezan, Jean-Francois Bhattacharyya, Shuvra S. UBL INSA Rennes IETR Rennes France Inst Pascal Aubiere France Scuola Super Sant Anna Pisa Italy Univ Maryland College Pk MD 20742 USA Salzburg Univ Appl Sci Salzburg Austria Tampere Univ Technol Tampere Finland

ISBN: (纸本)9781509033614

The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communicationrelated part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.

关键词： Software design

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Integer fast wavelet transform and its VLSI implementation for low power applications 16

Integer fast wavelet transform and its VLSI implementation f...

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ieee workshop on signal processing systems (sips 02)

作者： Dang, PP Chau, PM Univ Calif San Diego ECE Dept La Jolla CA 92093 USA

ISBN: (纸本)0780375874

This paper presents a new approach to the design of integer wavelet filters and an efficient VLSI architecture for low power implementation. Instead of using the lifting scheme, power-of-two wavelet coefficients are derived directly from the roots of the half-band filter. Based on the integer wavelets, we introduce a fast integer Discrete Wavelet Transformation (IntDWT). The proposed integer transform for (9,7) filters requires only 17 integer additions and 15 shift operations. It, however, achieves the same coding efficiency as the floating-point approach. In the proposed VLSI architecture, several optimization techniques are used to remove the redundancy of computational units along the data path. The hardware and software simulation results show that both high performance and low power consumption for DWT chipset can be accomplished at the algorithm architecture level.

关键词： Computational modeling Computer architecture Discrete transforms Discrete wavelet transforms Filters Hardware Software performance Very large scale integration Wavelet coefficients Wavelet transforms

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Subword parallel GF(2^m) ALU:: An implementation for a cryptographic processor

Subword parallel GF(2<SUP>m</SUP>) ALU:: An implementation f...

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ieee workshop on signal processing systems

作者： Lim, WM Benaissa, M Univ Sheffield Dept Elect & Elect Engn Sheffield S1 3JD S Yorkshire England

ISBN: (纸本)0780377958

This paper describes a subword parallel ALU for applications which require operations over GF(2(m)) and an implementation in the domain of cryptography. It has a reconfigurable datapath that allows it to operate in either a Single Instruction Multiple Data mode (SIMD, p GF(2(r)) operations r less than or equal to q) or a Single Instruction Single Data mode (SISD, one GF(2(r)) operation, where q < r less than or equal to m, m = p.q). The dual mode of the ALU allows efficient programming of Rijndael AES and Elliptic Curve Cryptography (ECC) (both of which use GF(2(m)) arithmetic, but have a large data size mismatch) on the same processor. This means better resource utilization of the processor which is doubly important for area constrained implementations. An FPGA prototype of the processor has been built and tested successfully for AES and elliptic curve operations.

关键词： Circuits Data security Digital arithmetic Elliptic curve cryptography Elliptic curves Field programmable gate arrays Galois fields Prototypes Reed-Solomon codes Resource management

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Sequential Polarization Imaging Using Multi-View Fusion

Sequential Polarization Imaging Using Multi-View Fusion

引用

ieee International workshop on signal processing systems (sips)

作者： Richter, Thomas Genser, Nils Seiler, Juergen Kaup, Andre Saloman, Christopher Kasnakli, Koray Nowak, Arne Schoeberl, Michael Friedrich Alexander Univ Erlangen Nurnberg Multimedia Commun & Signal Proc Cauerstr 7 D-91058 Erlangen Germany Fraunhofer Inst Integrated Circuits IIS Elect Imaging Dept Wolfsmantel 33 D-91058 Erlangen Germany

ISBN: (纸本)9781538604465

Multi-channel imaging like RGB is common today, however, a custom configuration of other modalities, such as wavelengths or polarization, is expensive and often unavailable. We propose a novel configurable multi-modal imaging system that solves this problem by using off-the-shelf components and proper fusion algorithms. The paper shows the application of polarization imaging for machine vision inspection. Sequential images acquired with different cameras and polarization angles are first registered and then fused together. With standard components, we demonstrate a superior image quality to existing specialized cameras while being significantly cheaper, available, and easily configurable.

关键词： Cameras Feature extraction Image registration Inspection Wheels Glass

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