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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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FPGA implementation of a Multi-Channel Continuous-Throughput FFT Processor

FPGA Implementation of a Multi-Channel Continuous-Throughput...

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Fankhauser, Elia Wassner, Juergen Lucerne Univ Appl Sci & Arts RSLUR Intelligent Sensors & Networks Lab ISN Luzern Switzerland

ISBN: (纸本)9781538663189

The Fast Fourier Transform (FFT) is at the heart of many signal processing systems, e.g. those using orthogonal frequency-division multiplexing (OFDM) modulation. For such systems the FFT is typically implemented on dedicated hardware, e.g. field-programmable gate arrays (FPGAs), to meet the high throughput and latency requirements. This paper describes a 2 parallel radix-2 FFT core embedded into an overall processing architecture that allows data interfaces to be tailored to application specific needs. The proposed solution can dynamically switch between different FFT sizes while maintaining its maximum theoretical throughput. Our experiments show that a two-fold increase in throughput can be achieved without doubling resource usage, when taking into account FPGA-specific features for several optimizations.

关键词： FFT FPGA Throughput Butterfly

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design of DSP instructions and their hardware architecture for a Reed-Solomon codec 16

Design of DSP instructions and their hardware architecture f...

引用

ieee workshop on signal processing systems (sips 02)

作者： Lee, JS Sunwoo, MH Oh, SK Ajou Univ Sch Elect & Comp Engn Paldal Ku Suwon 442749 South Korea

ISBN: (纸本)0780375874

This paper presents new DSP (Digital signal Processor) instructions and their hardware architecture to implement efficiently RS (Reed-Solomon) encoding and decoding, which is one of the most widely used FEC (Forward Error Control) algorithms. The proposed DSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware architecture perform GF (Galois Field) operations using the proposed GF multiplier and adder. There ore, the proposed DSP architecture can significantly reduce the number of clock cycles compared with existing DSP chips. It can perform RS decoding at a rate of up to 175.5 Mbps on 100MHz DSP chips.

关键词： Codecs Decoding Digital signal processing Digital signal processing chips Digital signal processors Encoding Error correction Forward error correction Hardware Reed-Solomon codes

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Cross-layer energy-throughput evaluation of multi-hop/path communication and link adaptation for ieee 802.11a.

Cross-layer energy-throughput evaluation of multi-hop/path c...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Pollin, S Goyens, R Cleeren, W Bougard, B Catthoor, F Van der Perre, L Moerman, I IMEC B-3001 Louvain Belgium

ISBN: (纸本)0780393333

Future wireless communication devices are expected to support a wide range of applications, while coping with stringent energy budget requirements. Delivering at each moment in time the required performance with minimal energy consumption is a promising energy management technique to enable pervasive wireless networking. Considering transmission energy only, the use of multiple small hops results in a decrease of the energy consumption. On the other hand, decreasing the transmission rate of a single hop similarly results in a decrease of the energy needed to deliver a bit. In this paper we compare the use of multiple small hops along different paths with a single large hop in the Energy-Throughput design space. In contrast with earlier work, realistic transceiver models are used, that cover the complete MAC, transmit and receive chain and support different transmission rates. Results show that, compared to single hop link adaptation, the use of multiple hops in indoor environments is only optimal in the Energy-Throughput space for distances larger than 30m or when there are obstacles present that can be avoided in alternative paths. For those larger distances, significant gains are possible though. Hence, to achieve energy optimal operation in 802.11a networks, it is important to adapt jointly the physical layer constellation and network layer path selection.

关键词： energy efficiency multi-hop communication 802.11a WLAN cross-layer research

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Adaptive bit-width compression for low-energy frame memory design

Adaptive bit-width compression for low-energy frame memory d...

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ieee workshop on signal processing, systems design and implementation (sips 01)

作者： Moshnyaga, VG Fukuoka Univ Dept Elect Engn & Comp Sci Fukuoka 8140180 Japan

ISBN: (纸本)0780371453

A now architectural technique to reduce energy dissipation of frame memory is proposed. Unlike existing approaches, the technique exploits the pixel correlation in video sequences, dynamically adjusting the memory bit-width to the number of bits changed per pixel. Instead of treating the data bits independently, we group the most significant bits together, activating the corresponding group of bit-lines adaptively to data variation. The method is not restricted to the specific bit-patterns nor depends on the storage phase. It works equally well on read and write accesses. as well as during precharging. Simulation results show that using this method we can reduce the total energy consumption of frame memory by 20% without affecting the picture quality.

关键词： Image compression

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A flexible multiplier for media processing

A flexible multiplier for media processing

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Brunelli, Claudio Salmela, Perttu Takala, Jarmo Nurmi, Jari Institute of Digital and Computer Systems Tampere University of Technology P.O.Box 553 Tampere FIN-33101 Finland

ISBN: (纸本)0780393341

In the last years multimedia processing applications have gained more and more importance in the field of mobile and hand-held devices, requiring dedicated hardware platforms characterized by high performance computation capabilities with reduced area occupation and low power consumption. 2D graphics and signal processing applications in general benefit from the usage of integer Single-Instruction-Multiple-Data (SIMD) functional units, while 3D graphics applications can be significantly accelerated employing single precision floating-point functional units. This paper presents a model and implementation of a versatile multiplier able to perform either double precision, (paired) single precision floating-point multiplications or 16-bit or 8-bit SIMD integer (vector) multiplications;it was implemented on an FPGA device and compared to other floating-point multipliers and similar devices, each capable of performing only a limited subset of the proposed design. The results show that all the functionalities provided by the set of the other considered devices can be performed by the proposed design with a minor area overhead penalty and still competitive performance;thus the proposed multiplier represents in particular a good candidate for usage in area-limited designs. © 2005 ieee.

关键词： Multimedia systems

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Contrastive Learning in Memristor-based Neuromorphic systems 37

Contrastive Learning in Memristor-based Neuromorphic Systems

引用

2024 International workshop on signal processing systems

作者： Merkel, Cory Ororbia, Alexander G. Rochester Inst Technol Brain Lab Rochester NY 14623 USA Rochester Inst Technol Neural Adapt Comp Lab Rochester NY 14623 USA

ISBN: (纸本)9798350373769;9798350373752

Spiking neural networks have become an important family of neuron-based models that sidestep many of the key limitations facing modern-day backpropagation-trained deep networks, including their high energy inefficiency and long-criticized biological implausibility. In this work, we design and investigate a proof-of-concept instantiation of contrastive-signal-dependent plasticity (CSDP), a neuromorphic form of forward-forward-based, backpropagation-free learning. Our experimental simulations demonstrate that a hardware implementation of CSDP is capable of learning simple logic functions without the need to resort to complex gradient calculations.

关键词： conrastive learning hebbian memristor neuromorphic

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The high throughput and low memory access design of sub-pixel interpolation for H.264/AVC HDTV decoder

The high throughput and low memory access design of sub-pixe...

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Li, Mo Wang, Ronggang Wu, Chen VLSI System Laboratory Beijing University of Technology Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)0780393341

In this paper, we proposed a parallel and pipeline architecture for the sub-pixel interpolation filter in H.264/AVC conformed HDTV decoder. To efficiently use the bus bandwidth, we bring forward two memory access optimization strategies to avoid redundant data transfer and improve data bus utilization. To improve the processing throughput, we use parallel and multi-stage pipeline architecture for conducting data transmission and interpolation filtering in parallel. As compared to the traditional designs, our scheme offers 60% reduced memory data transfer. While clocking at 66MHz, our design can support 1280x720@30Hz processing throughput. The proposed design is suitable for system-on-chip design. © 2005 ieee.

关键词： High definition television

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A combined 16-bit binary and dual galois field multiplier 16

A combined 16-bit binary and dual galois field multiplier

引用

ieee workshop on signal processing systems (sips 02)

作者： Garria, J Schulte, MJ Lehigh Univ Dept Comp Sci & Engn Bethlehem PA 18015 USA

ISBN: (纸本)0780375874

Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit two's complement or unsigned multiplication, or two independent 8-bit GF(28) multiplications in SIMD fashion. The combined multiplier is designed by modifying a conventional binary tree multiplier. It uses a novel wiring methodology to provide two simultaneous GF(28) multiplies with a minor impact on area and delay. Two alternatives for the multiplier design are presented. Area and delay estimates indicate that compared to a conventional binary tree multiplier, the combined multiplier has roughly 6% more delay and 23% more area.

关键词： Binary trees Computer science Delay estimation Digital arithmetic Digital signal processing Encoding Galois fields Hardware Polynomials Reed-Solomon codes

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Efficient Pseudo-Noise sequence generation for spread-spectrum applications 16

Efficient Pseudo-Noise sequence generation for spread-spectr...

引用

ieee workshop on signal processing systems (sips 02)

作者： Sriram, S Sundararajan, VA Texas Instruments Inc Wireless Infrastruct Syst Dallas TX 75265 USA

ISBN: (纸本)0780375874

Novel approaches for Linear Feedback Shift Register based Pseudo Noise generators are presented. Area-delay tradeoff between the various approaches is also presented. The principle approaches that are studied in this paper include 1) State-transition matrix based approaches, 2) State-transition matrix based approaches with lookahead, 3) State storage based approaches and 4) Polynomial multiplication based approaches. Synthesis results are also provided to illustrate the area/delay trade-offs.

关键词： Base stations Clocks Delay lines Linear feedback shift registers Multiaccess communication Polynomials Propagation delay Shift registers signal generators Spread spectrum communication

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design of Iterative Hybrid Beamforming for Multi-User mmWave Massive MIMO systems

Design of Iterative Hybrid Beamforming for Multi-User mmWave...

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Tsai, Pei-Yun Huang, Xiao-Sheng Natl Cent Univ Dept Elect Engn Taoyuan Taiwan

ISBN: (纸本)9781538663189

Hybrid beamforming that combines analog phase shift and digital processing is a promising solution to alleviate the implementation cost and power consumption in millimeter wave (mmWave) massive MIMO systems. To achieve sum rate optimization, an iterative scheme that considers both the analog and digital precoders in the optimization metric is proposed. The digital precoder is mainly used to remove multiple access interference for enhancing the multiplexing gain. Then, the coordinated beamforming procedure between the base station and mobile stations is performed to exploit the array gain. Although the iterative scheme is used, only few iterations are required. This scheme can also be extended to the systems using precoding and combining vectors from quantized codebooks. Furthermore, with the channel reciprocity property or the two-phase training strategy, the iterative scheme can obtain the required channel information. From the simulation results, the sum rate is improved, especially when quantized codebooks are used.

关键词： Hybrid beamforming massive MIMO multi-user iterative algorithm codebook

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