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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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design of Iterative Hybrid Beamforming for Multi-User mmWave Massive MIMO systems

Design of Iterative Hybrid Beamforming for Multi-User mmWave...

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Tsai, Pei-Yun Huang, Xiao-Sheng Natl Cent Univ Dept Elect Engn Taoyuan Taiwan

ISBN: (纸本)9781538663189

Hybrid beamforming that combines analog phase shift and digital processing is a promising solution to alleviate the implementation cost and power consumption in millimeter wave (mmWave) massive MIMO systems. To achieve sum rate optimization, an iterative scheme that considers both the analog and digital precoders in the optimization metric is proposed. The digital precoder is mainly used to remove multiple access interference for enhancing the multiplexing gain. Then, the coordinated beamforming procedure between the base station and mobile stations is performed to exploit the array gain. Although the iterative scheme is used, only few iterations are required. This scheme can also be extended to the systems using precoding and combining vectors from quantized codebooks. Furthermore, with the channel reciprocity property or the two-phase training strategy, the iterative scheme can obtain the required channel information. From the simulation results, the sum rate is improved, especially when quantized codebooks are used.

关键词： Hybrid beamforming massive MIMO multi-user iterative algorithm codebook

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An Efficient implementation of LDPC Decoders on ARM Processors

An Efficient Implementation of LDPC Decoders on ARM Processo...

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Liu, Bing Liu, Rongke Liu, Zhanxian Zhao, Ling BeiHang Univ Sch Elect & Informat Engn Beijing Peoples R China

ISBN: (纸本)9781538663189

In this paper, we present an ARM based decoder for Low Density Parity Check (LDPC) codes. To maximize the efficiency of the parallel execution and fully utilize the ARM processors' capacity, instruction-level parallelism optimizations are applied. Compression storage and efficient data prefetching optimizing methods are used to enhance the memory cache efficiency. The experiments are carried out on NVIDIA Jetson K1 platform. Our decoder can achieve 1.85 times speed up compared with the related work. And the decoder has better energy efficiency comparing to the decoders on x86-CPU and GPU.

关键词： Decoding Throughput Program processors Parity check codes Pipelines Neon Optimization

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A low cost packet detector in OFDM-based ultra-wideband systems

A low cost packet detector in OFDM-based ultra-wideband syst...

引用

ieee workshop on signal processing systems design and implementation

作者： Lai, Jyh-Ting Chu, Chun-Yuan Wu, An-You Chen, Wen-Chiang Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Faraday Technology Corporation

ISBN: (纸本)9781424403820

Multiband orthogonal frequency-division multiplexing (MB-OFDM) systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate packet detector (PD) in terms of the requirement for the high hardware complexity. In this paper, we propose several low-cost design schemes for the PD, such as Walsh-Hadamard decomposition, buffered summation, and sign-bit-remaining methods. The estimated gate count of the resulting implemented PD is less than half that of existing solutions.

关键词： Orthogonal frequency division multiplexing

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Parallel interleaving on parallel DSP architectures 16

Parallel interleaving on parallel DSP architectures

引用

ieee workshop on signal processing systems (sips 02)

作者： Richter, T Fettweis, GP Tech Univ Dresden Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)0780375874

Today's communications systems especially in the field of wireless communications rely on many different algorithms to provide applications with constantly increasing data rates and higher quality. This development combined with the wireless channel characteristics as well as the invention of turbo codes has particularly increased the importance of interleaver algorithms. In this paper we demonstrate the feasibility to exploit the hardware parallelism in order to accelerate the interleaving procedure. Based on a heuristic algorithm the possible speedup for different interleavers as a function of the degree of parallelism of the hardware is presented. The parallelization is generic in the sense that the assumed underlying hardware is based on a parallel datapath DSP architecture and therefore provides the flexibility of software solutions.

关键词： Decoding Delay Digital signal processing Digital video broadcasting Hardware Heuristic algorithms Interleaved codes Mobile communication signal processing algorithms Turbo codes

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Adaptive filter and adaptive linear Fourier combined in processing of cognitive-event-related potential

Adaptive filter and adaptive linear Fourier combined in proc...

引用

ieee Annual workshop on signal processing systems: design and implementation

作者： Vasile, D Vasile, D Puscasu, V Foca, E So Methodist Univ Sch Engn & Appl Sci Dallas TX 75275 USA

ISBN: (纸本)0780364880

This paper focuses on estimating the evoked potentials (EP) signal recorded from human scalp that occurs in response to an externally applied stimulus, A Fourier series model for time-varying EP is chosen here. The model parameters are estimated by an RLS adaptive procedure, enabling the estimator efficiency track clinically significant alteration in the EP.

关键词： Adaptive filtering

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Stochastic implementation of the Disparity Energy Model for Depth Perception

Stochastic Implementation of the Disparity Energy Model for ...

引用

ieee International workshop on signal processing systems (sips)

作者： Boga, Kaushik Onizawa, Naoya Leduc-Primeau, Francois Matsumiya, Kazumichi Hanyu, Takahiro Gross, Warren J. McGill Univ Dept Elect & Comp Engn Montreal PQ Canada Tohuku Univ Sendai Miyagi Japan

ISBN: (纸本)9781467396042

We implement a binocular vision system based on a disparity-energy model that emulates the hierarchical multilayered neural structure in the primary visual cortex. Layer 1 performs difference-of-Gaussian filtering that mimicks the center-surround receptive fields (RF) in the retina, layer 2 performs Gabor filtering mimicking the orientation selective filtering performed by simple cells and layer 3 has complex cells tuned to detecting 5 different disparities. A VLSI architecture is developed based on stochastic computing that is compact and adder-free. Even with a short stream length, the proposed architecture achieves better disparity detection than a floating-point version by using a modified disparity-energy model. A 1 x 100 pixel processing system is synthesized using TSMC 65nm CMOS technology and achieves up to 79% reduction in area-delay product compared to a fixed point implementation.

关键词： ENERGY MODELS Depth Perception layer 3 Fixed point Stochastic gabor filtering Gauss Filtration

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Arbitration schemes synthesis approach for multiprocessor systems

Arbitration schemes synthesis approach for multiprocessor sy...

引用

1998 ieee workshop on signal processing systems - design and implementation (sips'98)

作者： Zitouni, A Abid, M Tourki, R Fac Sci Elect & Microelect Lab Monastir 5019 Tunisia

ISBN: (纸本)0780349970

The aim of this paper is to present an arbiter synthesis approach stated as an arbitration scheme generation/selection problem. This approach may be easily inserted in an extendible system co-design methodology. It assumes that many co-design tasks have been performed, and it aims to automate the resolution of the access conflict problem that may be inevitably encountered whenever there is a resource contention in the system. The proposed approach allows to transform a system composed of high level processes that share the same channels and the same variables in disordered manner into a set of processes executed by interconnected processors and hardware devices (e.g. ASICs, FPGAs, etc.) that share the same resources such as memories and busses using the most efficient arbitration scheme. This approach is basically based on an algorithm that allows respectively the automatic generation/selection of the arbitration scheme, and the fixed priority assignment in a manner that minimizes the real time cost.

关键词： arbiter synthesis hardware/software co-design communication synthesis high-level synthesis

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Efficient Near-MMSE Detector for Large-Scale MIMO systems

Efficient Near-MMSE Detector for Large-Scale MIMO Systems

引用

ieee International workshop on signal processing systems (sips)

作者： Wu, Zhizhen Ge, Lulu You, Xiaohu Zhang, Chuan Southeast Univ Lab Efficient Architectures Digital Commun & Sign Nanjing Jiangsu Peoples R China Southeast Univ Natl Mobile Commun Res Lab Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781538604465

In this paper, an improved and low-complexity signal detection approach for large-scale multiple-input multiple-output (MIMO) systems has been proposed. This approach utilizes the preconditioning technique to accelerate the conventional detection algorithm based on Gauss-Seidel (GS) iterative method, and achieves a detection performance close to the minimum mean square error (MMSE) detection algorithm with relatively small iteration counts. It also outperforms the counterparts based on the Neumann series (NS) expansion and the conjugate gradient (CG) method in poor propagation environments, such as MIMO systems with large loading or correlated factors. The corresponding architecture is also proposed with both novelty and scalability. It takes advantage of the cyclic-shift property of the GS method, and therefore facilitates the hardware implementation. Both numerical results and complexity analysis demonstrate that the proposed detector is efficient and suitable for large-scale MIMO systems.

关键词： Large-scale MIMO linear MMSE detection Gauss-Seidel (GS) method preconditioning VLSI architecture

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An Area Efficient Real- and Complex-Valued Multiply-Accumulate SIMD Unit for Digital signal Processors

An Area Efficient Real- and Complex-Valued Multiply-Accumula...

引用

ieee International workshop on signal processing systems (sips)

作者： Gerlach, Lukas Paya-Vaya, Guillermo Blume, Holger Leibniz Univ Hannover Inst Microelect Syst Cluster Excellence Hearing4all Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9781467396042

This paper explores a real-and complex-valued multiply-accumulate (MAC) functional unit for digital signal processors. MAC units with single-instruction-multiple-data (SIMD) support are often used to increase the processing performance in modern signal processing processors. Compared to a realvalued SIMD-MAC units, the proposed unit uses the same multipliers to also support complex-valued SIMD-MAC and butterfly operations. The area overhead for the complex mode is small. Complex-valued operations speed up signal processing algorithms and make the execution more efficient in terms of power consumption. As a case study, a fast Fourier transform (FFT) is implemented for a VLIW-processor with a complex-valued SIMD butterfly extension. The proposed functional unit is quantitatively evaluated in terms of performance, silicon area, and power consumption.

关键词： Digital signal processors Power consumption single instruction multiple datastream signal processor signal processing algorithms FUNCTIONAL UNITS Fast Fourier transform MAXIMUM ACCEPTABLE CONTAMINATION Media Access Protocol Butterfly

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A Formal design Methodology for Synthesizing a Clock signal with an Arbitrary Duty Cycle of M/N

A Formal Design Methodology for Synthesizing a Clock Signal ...

引用

ieee International workshop on signal processing systems (sips)

作者： Ge, Lulu Zhang, Chuan Zhong, Zhiwei You, Xiaohu Southeast Univ Natl Mobile Commun Res Lab Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781467396042

Nowadays, the emerging research topic on synthesizing logic functions with chemical reaction networks (CRNs) have drawn intensive attentions from both academia and industry. By making use of its advantages in power, spontaneity, robustness, and parallelization, a lot of amazing applications of this research topic have been proposed and therefore give this field a promising future. However, in order to properly synthesize sequential logics with CRNs, the difficulties in construct a clock signal with an arbitrary duty cycle turns out to be a bottleneck. To this end, this paper devotes itself in constructing a formal design methodology, which can conveniently generate clock signals with any duty cycle of M/N. In order to achieve this goal, we put our efforts in steps. First, clock signal with duty cycle of 1/N with N >= 3 is introduced. Then, the case of 1/2 duty cycle is taken care of. Finally, clock signal with duty cycle of M/N is constructed in a nice manner with the aid of circle map representation.

关键词： Clock signal chemical reaction networks (CRNs) synthetic biology molecular computing sequential logic

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