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Digital signal processing challenges in MIMO wireless communications

Digital signal processing challenges in MIMO wireless commun...

引用

ieee workshop on signal processing systems- design and implementation-(sips) 2001

作者： Boelcskei, H. Univ. Illinois at Urbana-Champaign Urbana-Champaign IL United States

The requirements on data rate and quality of service of future wireless communications systems call for new digital signal processing techniques to increase spectrum efficiency and improve link reliability. Deploying multiple antennas at both transmitter and receiver of a wireless link (MIMO technology) has the potential to achieve these ambitious goals. MIMO techniques are starting to find their way into standards, such as UMTS and ieee 802.16. This talk gives an overview of MIMO wireless covering issues such as propagation models, broadband transceivers, signaling techniques and coding and modulation. Special emphasis is put on the digital processing aspects.

关键词： Digital signal processing

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AN IMPROVED MIN-SUM BASED COLUMN-LAYERED DECODING ALGORITHM FOR LDPC CODES

AN IMPROVED MIN-SUM BASED COLUMN-LAYERED DECODING ALGORITHM ...

引用

ieee workshop on signal processing systems (sips 2009)

作者： Lin, Jun Sha, Jin Wang, Zhongfeng Li, Li Nanjing Univ Inst VLSI Design Nanjing 210093 Jiangsu Peoples R China Broadcom Corp Irving TX 92617 USA

ISBN: (纸本)9781424443345

Low-Density Parity-Check code is a kind of near-optimal error correction code. Developing a highly efficient decoding algorithm is the main challenge of the implementation of LDPC code. In this paper, based on the min-sum column-layered decoding algorithm, a new selective computation technique is proposed to reduce the number of comparisons. With the presented decoding algorithm, the total number of floating number comparisons can be reduced dramatically (range from 81% to 91%) at the cost of negligible hardware overhead. Simulation results show that the decoding performance and iteration times are almost the same as the original column-layered decoding algorithm.

关键词： Low-density parity-check (LDPC) codes column-layered decoding shuffled decoding error correction codes VLSI

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design space exploration of streaming multiprocessor architectures 16

Design space exploration of streaming multiprocessor archite...

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ieee workshop on signal processing systems (sips 02)

作者： Zivkovic, VD Deprettere, E van der Wolf, P de Kock, E Leiden Univ LIACS NL-2333 CA Leiden Netherlands

ISBN: (纸本)0780375874

In this paper, we present a comparison of two design-space exploration approaches. The comparison is in terms of (1) speed of simulation versus accuracy of performance numbers, and (2) connection to trajectories for detailed design. The two approaches are: The trace driven approach and the control data flow graph approach. The first approach leads to the shortest simulation time, but is insufficiently accurate in the performance numbers it provides. It also does not connect well to a trajectory for detailed design. The second method is leading to rather long simulation times, yet it can give fairly accurate performance numbers, and it produces results that can be readily taken as input for further design. The two approaches are somehow extreme in that several in-between methods can be conceived of. We also describe our search for an exploration trajectory which would be somehow "optimal" in terms of speed versus accuracy and closeness to a design trajectory. As expected, this trajectory appears somewhere in-between the two extremes mentioned above.

关键词： Concurrent computing Costs Flow graphs Laboratories Performance analysis Power dissipation signal design signal processing Space exploration System-on-a-chip

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LOW-POWER HETEROGENEOUS COMPUTING VIA ADAPTIVE EXECUTION OF DATAFLOW ACTORS

LOW-POWER HETEROGENEOUS COMPUTING VIA ADAPTIVE EXECUTION OF ...

引用

ieee International workshop on signal processing systems (sips)

作者： Boutellier, Jani Bhattacharyya, Shuvra S. Tampere Univ Technol Lab Pervas Comp Tampere Finland Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

ISBN: (纸本)9781538604465

Dataflow models of computation have been shown to provide an excellent basis for describing signal processing applications and mapping them to heterogeneous computing platforms that consist of multicore CPUs and graphics processing units (GPUs). Recently several efficient dataflow-based programming frameworks have been introduced for such needs. Most of contemporary signal processing applications can be described using static dataflow models of computation (e.g. synchronous dataflow) that have desirable features such as compile-time analyzability. Unfortunately, static dataflow models of computation turn out to be restrictive when applications need to adapt their behavior to varying conditions at run-time, such as power saving through adaptive processing. This paper analyzes three dataflow approaches for implementing adaptive application behavior in terms of expressiveness and efficiency. The focus of the paper is on heterogeneous computing platforms and particularly on adapting application processing for achieving power saving. Experiments are conducted with deep neural network and dynamic predistortion applications on two platforms: a mobile multicore SoC and a GPU-equipped workstation.

关键词： Dataflow computing signal processing parallel processing graphics processing units deep neural networks

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implementation strategy of MPEG-2 audio decoder and efficient multichannel architecture

Implementation strategy of MPEG-2 audio decoder and efficien...

引用

Proceedings of the 1997 ieee workshop on signal processing systems, sips 97: design and implementation

作者： Tsai, Tsung-Han Chen, Liang-Gee Chen, Ruei-Xi Natl Taiwan Univ Taipei Taiwan

The paper describes an MPEG-2 audio decoder applied in multichannel extension. In the analysis of intelligent implementation strategy, the decoder can be divided into two hardware-oriented architecture stages. Also, an efficient architecture for multichannel processor is presented. The decoder is developed for the approach for simplicity and low-cost design.

关键词： Digital signal processing

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Parallelization of Kvazaar HEVC Intra Encoder for Multi-core Processors

Parallelization of Kvazaar HEVC Intra Encoder for Multi-core...

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ieee International workshop on signal processing systems (sips)

作者： Koivula, Ari Viitanen, Marko Vanne, Jarno Hamalainen, Timo D. Fasnacht, Laurent Tampere Univ Technol Dept Pervas Comp Tampere Finland Ecole Polytech Fed Lausanne EPFL SCI STI MM Lausanne Switzerland

ISBN: (纸本)9781467396042

This paper introduces key parallelization strategies of our Kvazaar HEVC intra encoder for multicore processors. The schemes implemented in Kvazaar are 1) tiles;2) Wavefront Parallel processing (WPP);and 3) picture-level parallel processing. Kvazaar is the only practical open-source HEVC encoder that supports all these schemes. In addition, its ratedistortion-complexity characteristics are superior to other public implementations in all-intra (AI) coding. Our experiments with high-quality encoder presets show that a C implementation of Kvazaar is 19% faster than the corresponding implementation of x265 for the same coding efficiency with 8 threads and 38% faster with 16 threads. With the high-speed presets, Kvazaar improves coding efficiency by 4.5% while being twice as fast as x265. The high-speed preset of Kvazaar obtains almost the same coding efficiency as the high-quality preset of f265 while being 24 times faster when 16 threads are used.

关键词： HEVC intra coding Kvazaar HEVC encoder tiles Wavefront Parallel processing (WPP)

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A real time, low latency, hardware implementation of the 2-D discrete wavelet transformation for streaming image applications

A real time, low latency, hardware implementation of the 2-D...

引用

ieee workshop on signal processing systems

作者： Benderli, O Tekmen, YC Ismailoglu, N Middle E Tech Univ TUBITAK BILTEN TR-06531 Ankara Turkey

ISBN: (纸本)0780377958

In this paper, we present a 2-D Discrete Wavelet Transformation (DWT) hardware for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n(1) x n(2) size image processed using (n(1)/k(1)) x (n(2)/k(2)) sized tiles the latency is equal to the time elapsed to accumulate a (1/k(1)) portion of one image. In addition, a (2/k(1)) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003.

关键词： Bandwidth Delay Discrete wavelet transforms Field programmable gate arrays Filters Hardware Low earth orbit satellites Streaming media Tiles Transform coding

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VLSI implementation-oriented (3, k)-regular low-density parity-check codes

VLSI implementation-oriented (3, <i>k</i>)-regular low-densi...

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ieee workshop on signal processing, systems design and implementation (sips 01)

作者： Zhang, T Parhi, KK Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)0780371453

In the past few years, Gallager's Low-Density Parity-Check (LDPC) codes received a lot of attention and many efforts have been devoted to analyze and improve their error-correcting performance. However, little consideration has been given to the LDPC decoder VLSI implementation. The straightforward fully parallel decoder architecture usually incurs too high complexity for many practical purposes and should be transformed to a partly parallel realization. Unfortunately, due to the randomness of LDPC codes, it's nearly impossible to develop an effective transformation for an arbitrary given LDPC code. In this paper, we propose a joint code and decoder design approach to construct a class of (3, k)-regular LDPC codes which exactly fit to a partly parallel decoder implementation and have a very good performance. Moreover, for such LDPC codes, we propose a systematic efficient encoding scheme by effectively exploiting the sparseness of its parity check matrix.

关键词： Codes (symbols)

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Analysing the Performance of Divide-and-Conquer Sequential Matrix Diagonalisation for Large Broadband Sensor Arrays

Analysing the Performance of Divide-and-Conquer Sequential M...

引用

ieee International workshop on signal processing systems (sips)

作者： Coutts, Fraser K. Thompson, Keith Weiss, Stephan Proudler, Ian K. Univ Strathclyde Dept Elect & Elect Engn Glasgow Lanark Scotland Loughborough Univ Technol Sch Elect Elect & Syst Engn Loughborough Leics England

ISBN: (纸本)9781538604465

A number of algorithms capable of iteratively calculating a polynomial matrix eigenvalue decomposition (PEVD) have been introduced. The PEVD is an extension of the ordinary EVD to polynomial matrices and will diagonalise a parahermitian matrix using paraunitary operations. Inspired by recent work towards a low complexity divide-and-conquer PEVD algorithm, this paper analyses the performance of this algorithm - named divide-and-conquer sequential matrix diagonalisation (DC-SMD) - for applications involving broadband sensor arrays of various dimensionalities. We demonstrate that by using the DC-SMD algorithm instead of a traditional alternative, PEVD complexity and execution time can be significantly reduced. This reduction is shown to be especially impactful for broadband multichannel problems involving large arrays.

关键词： Matrix decomposition Approximation algorithms Complexity theory Broadband communication signal processing algorithms Covariance matrices Eigenvalues and eigenfunctions

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Low power techniques for MP3 audio decoder using subband cut-off approach

Low power techniques for MP3 audio decoder using subband cut...

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sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Tsai, Tsung-Han Wang, Chun-Kai Liu, Chun-Nan Department of Electronic Engineering National Central University Chung-Li Taiwan

ISBN: (纸本)0780393341

In this paper low power techniques for MP3 audio decoder are used based on a phenomenon of zero-filled subbands. By our analysis, large part of subbands contains useless zero-valued data, which can be cut-off. We propose an effective architecture to gain incremental improvements in power consumption and computation complexity. In DWIMDCT block, the computational complexity can be reduced to 34% when we combine the subband cut-off technique and our proposed fast algorithm. In SIMDCT block of Synthesis filterbank, the same technique can be applied and the computational complexity can be reduced to 17%. This subband cut-off approach is simple and can be easily integrated with other designs. © 2005 ieee.

关键词： Audio systems

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