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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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Run-time reconfigurable adaptive signal processing system with asynchronous dynamic pipelining: A case study of DLMS ADFE

Run-time reconfigurable adaptive signal processing system wi...

引用

ieee workshop on signal processing systems design and implementation

作者： Chen, SZ Zhang, T Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY USA

ISBN: (纸本)0780385047

Most pipelined adaptive signal processing systems are inherently subject to a trade-off between throughput and signal processing performance because of the adaptation feedback loops. To mitigate this dilemma, we propose to apply asynchronous pipeline to implement pipelined adaptive signal processing systems that can support run-time reconfigurable throughput/performance trade-offs. This can be leveraged to improve the overall system performance in many applications. In this work, we demonstrate this design approach using a delayed LMS (DLMS) adaptive decision feedback equalizer (ADFE) for the communication links with variable data rate. By adjusting the pipelining depth on-the-fly, the DLMS ADFE can dynamically track the best equalization performance allowed by different data rate. We develop the design scheme that applies a zero-delay-overhead asynchronous pipeline style to implement ADFE and support dynamic pipelining depth control. Simulation result shows a significant performance improvement compared with its synchronous counterpart.

关键词： Adaptive systems

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A content quality driven energy management system for mobile 3D graphics

A content quality driven energy management system for mobile...

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Tack, Nicolaas Lafruit, Gauthier Catthoor, Francky Lauwereins, Rudy IMEC KU Leuven Leuven Belgium IMEC Leuven Belgium

ISBN: (纸本)0780393341

Today, mobile terminals such as Personal Digital Assistants and mobile phones have reached a sufficiently high level of performance as to support simple 3D Graphics applications. The challenge is to generate the best possible images within the performance constraints of the used terminal. The algorithms that solve this optimization problem however ignore the energy consumption, which is a scarce resource on a mobile device. We therefore propose to extend current 3D graphics optimization algorithms which adjust image quality to meet timing constraints, with an energy cost. We propose to let the user choose the desired trade-off between visual quality and energy consumption. The task of the optimization algorithm is then to try to provide the user requested quality and to minimize the energy consumption for a given execution time deadline. © 2005 ieee.

关键词： Mobile telecommunication systems

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Hardware Error Correction using Local Syndromes

Hardware Error Correction using Local Syndromes

引用

ieee International workshop on signal processing systems (sips)

作者： Hafidhi, Mohamed Mourad Boutillon, Emmanuel Univ Bretagne Sud UMR 6582 Lab STICC F-56100 Lorient France

ISBN: (纸本)9781538604465

Increasing the integration density offers the possibility for designers to built very complex system on a single chip. However, approaching the limits of integration, circuit reliability has emerged as a critical concern. The loss of reliability increases with process/voltage and temperature (PVT) variations. Faults can appear in circuits which can affect the system behaviour and lead to a system failure. Therefore it is increasingly important to build more fault tolerant resilient system. This paper 1 proposes a new fault tolerant scheme, the Duplication with Syndrome based Correction (DSC) scheme. Two criteria were considered to evaluate the proposed scheme: the reliability (probability that no error appears in the output of the architecture) and the hardware efficiency of the architecture. Results show that the DSC scheme reduces the complexity by 32%, compared to the classical Triple Modular Redundancy (TMR) scheme, while maintaining a level of reliability closed to the TMR. The paper shows also an example of signal processing applications where the DSC has been used to protect the correlation function and filters inside the tracking loops of the Global Positioning System (GPS) receiver.

关键词： Tunneling magnetoresistance Redundancy Integrated circuit reliability Circuit faults Fault tolerant systems

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implementation of high throughput soft output VITERBI decoders 16

Implementation of high throughput soft output VITERBI decode...

引用

ieee workshop on signal processing systems (sips 02)

作者： Yeo, E Augsburger, S Davis, WR Nikolic, B Univ Calif Berkeley Berkeley CA 94720 USA

ISBN: (纸本)0780375874

The architectural considerations for VLSI implementations of soft output Viterbi decoders are presented. Structural transformation of the add-compare-select structures provides high throughput with small area overhead. Modifications to the survivor memory unit and a comparison between the register exchange and memory traceback methods are highlighted. A 4mm(2) demonstration chip, consisting of two parallel, 8-state, 7-bit soft output Viterbi decoders, has been implemented in 0.18mum CMOS technology, and decodes at 500Mb/s with 1.8V supply. These decoders are used with Turbo codes, which have been demonstrated to achieve information rates close to the Shannon limit.

关键词： CMOS technology Convolutional codes Information rates Iterative decoding Magnetic recording Registers Throughput Turbo codes Very large scale integration Viterbi algorithm

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High-Throughput Decoding of Block Turbo Codes on Graphics processing Units

High-Throughput Decoding of Block Turbo Codes on Graphics Pr...

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ieee International workshop on signal processing systems (sips)

作者： Cho, Junhee Sung, Wonyong Seoul Natl Univ Dept Elect & Comp Engn 1 Gwanak Ro Seoul South Korea Samsung SDS Algorithm Res Team IoT Lab Seoul South Korea

ISBN: (纸本)9781538604465

Block turbo codes (BTCs) can provide very powerful forward error correction (FEC) for several applications, such as optical networks and NAND flash memory devices. These applications require soft-decision FEC codes to guarantee the bit error rate (BER) of under 10(-12), which is, however, very difficult to verify with a CPU simulator. In this paper, we present high throughput graphics processing unit (GPU) based turbo decoding software to aid the development of very low error rate BTCs. For effective utilization of the GPUs, the software processes multiple BTC frames simultaneously and minimizes the global memory access latency. Especially, the Chase-Pyndiah algorithm is efficiently parallelized to decode every row and column of a BTC word. The GPU-based simulator achieved the throughputs of about 80 and 150 Mb/s for decoding of BTCs composed of Hamming and BCH codes, respectively. The throughput results are up to 124 times higher when compared to the CPU-based ones.

关键词： Graphics processing unit

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implementation of the decorrelating transformation for low power fir filters

Implementation of the decorrelating transformation for low p...

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ieee workshop on signal processing systems design and implementation

作者： Erdogan, AT Arslan, T Lai, R Univ Edinburgh Sch Engn & Elect Edinburgh EH9 3JL Midlothian Scotland

ISBN: (纸本)0780385047

This paper presents the implementation of the decorrelating (DECOR) transformation technique for low power FIR filtering cores. The technique was introduced in the past, but was not fully evaluated for its area, delay and power performance. Early evaluations did not consider the whole implementation and were merely based on either some analytical methods or high level simulation models. This paper presents the complete VLSI implementation of the technique and a study of its area, delay and power performance with different order of coefficient differences and various multiplier types. We show that although the technique achieves up to 47% power saving in the multiplier unit, the overall power saving is up to 25% with up to 24% increase in area.

关键词： power consumption VLSI FIR filters decorrelation low-power electronics digital signal processing chips decorrelating transformation low power FIR filters VLSI implementation area performance delay performance power performance coefficient differences multiplier types power saving

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ieee 802.11ac MIMO receiver baseband processing on customized VLIW processor

IEEE 802.11ac MIMO receiver baseband processing on customize...

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2014 ieee workshop on signal processing systems, sips 2014

作者： Aghababaee Tafreshi, Mona Lehtonen, Lasse Levanen, Toni Valkama, Mikko Takala, Jarmo Tampere University of Technology Tampere Finland

ISBN: (纸本)9781479965885

In this paper, a software-based implementation for the Multiple Input and Multiple Output (MIMO) receiver baseband processing conforming to the ieee 802.11ac standard on a DSP core with vector extensions is presented. The implementation is carried out for different operation points including 2×2 and 4×4 MIMO configurations, yielding beyond 1Gbps transmission bit rate. This implementation mainly focuses on the frequency domain processing of the receiver. The presented solution is evaluated in terms of number of clock cycles and power consumption, and the feasibility of a real-time operation is then addressed and analyzed. If found feasible, such Software Defined Radio based solutions offer more flexibility and reduced time-to-market-cycles compared to the conventional solutions using fixed-function hardware platforms. © 2014 ieee.

关键词： Software radio

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On-line MSR-cordic VLSI architecture with applications to cost-efficient rotation-based adaptive filtering systems

On-line MSR-cordic VLSI architecture with applications to co...

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ieee workshop on signal processing systems design and implementation

作者： Yu, Tzu-Hao Yu, Chi-Li Jheng, Kai-Yuan Wu, An-Yeu Natl Taiwan Univ Grad Inst Elect Engn Dept Elect Engn Taipei 106 Taiwan

ISBN: (纸本)9781424403820

A novel on-line Mixed-Scaling-Rotation CORDIC (MSR-CORDIC) VLSI architecture is proposed. This architecture not only maintains the scaling-free property of the original,MSR-CORDIC, but also achieves the target of on-line angle computation. Compared with other existing CORDIC solutions, the proposed architecture is faster and more cost-efficient, especially for QRD-RLS filtering systems. Moreover, this on-line MSR-CORDIC can also be adopted by other rotation-based DSP applications.

关键词： Adaptive filtering

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design of a high-quality audio-specific DSP core

Design of a high-quality audio-specific DSP core

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Yoon, Suk Hyun Sunwoo, Myung Hoon Moon, Jong Ha School of Electrical and Computer Engineering Ajou University San 5 Wonchun-Dong Yeongtong-Ku Suwon 443-749 Korea Republic of LG Electronics Inc. 20 Yeouido-dong Yeongdeungpo-gu Seoul 150-721 Korea Republic of

ISBN: (纸本)0780393341

This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecure is specially designed and optimized for the IMDCT (Inverse Modified Discrete Cosine Transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 um standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz. © 2005 ieee.

关键词： Digital signal processing

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Utilizing synthesis methods in accurate system-level exploration of heterogeneous embedded systems

Utilizing synthesis methods in accurate system-level explora...

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ieee workshop on signal processing systems

作者： Erbas, C Pimentel, AD Univ Amsterdam Dept Comp Sci NL-1098 SJ Amsterdam Netherlands

ISBN: (纸本)0780377958

In this paper, we present anew mapping strategy for efficient design space exploration of heterogeneous embedded systems. The new mapping approach is developed within the context of the Sesame framework [16, 6] to improve its simulation accuracy and capabilities. In Sesame, separate application and architecture models together with an explicit mapping step are recognized within a system simulation. Originally, Sesame maps application models onto architecture models using trace-driven co-simulation of both models. However, this approach is limited by the fact that information is lost in the linear application traces that drive the architecture model. This may hamper accurate architecture simulation. The new mapping approach, which is based on Integer-controlled Dataflow actors, retrieves these limitations at the cost of a slight increase in complexity regarding the mapping. We compare our new approach with the current state-of-the-art mapping strategies under multiple criteria. Also with examples, we illustrate how we integrate our new mapping strategy into Sesame's mapping layer.

关键词： Computational modeling Computer science Context modeling Costs Embedded system Hardware Microprocessors Real time systems Space exploration Space technology

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