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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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Architecture-aware LDPC code design for software defined radio

Architecture-aware LDPC code design for software defined rad...

引用

ieee workshop on signal processing systems design and implementation

作者： Zhu, Yuming Chaki-Abarti, Chaitali Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

ISBN: (纸本)9781424403820

Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software defined radio (SDR) platform is likely to be inefficient. Our approach is to design the LDPC code to match the constraints imposed by the existing architecture, without compromising the communication performance. We present a procedure for architecture-aware code design that involves feature identification, code construction and verification. Details of the procedure for the case when the SDR platform is equipped with a multi-stage interconnection network (MIN) is presented. By analyzing the characteristics of the MIN, simple yet explicit constraints are derived and used in the code construction step. The resulting LDPC code can not only be mapped very efficiently onto the SDR platform but also has very good bit error rate (BER) performance.

关键词： Bit error rate

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Selective Tone Reservation for PAPR Reduction in Wireless Communication systems

Selective Tone Reservation for PAPR Reduction in Wireless Co...

引用

ieee International workshop on signal processing systems (sips)

作者： Ivanov, Andrey Lakontsev, Dmitry Skolkovo Inst Sci & Technol Moscow Russia

ISBN: (纸本)9781538604465

Orthogonal Frequency Division Multiplexing (OFDM) is a technique, which is widely used in 4G and considered in 5G wireless communication system these days. It is a form of multi-carrier modulation technique. One major disadvantage of OFDM is that the time domain OFDM signal leads to a high peak-to-average power ratio (PAPR). In this paper we propose a new selective tone reservation (STR) algorithm for reducing the PAPR in downlink channel of base station. We simulate the STR for different application scenarios with consideration of 4G/5G requirements. Simulation results show the STR has a PAPR reduction performance much better compared with all traditional methods in that it doesn't require any side information and has no effect on the performance of high order modulation users. Proposed method is fast and has an ultra-low latency compared with well-known iterative methods of tone reservation and constellation extension. Its performance is higher compared with a common clipping and filtering due to employing a constellation recognition technique for blind detection of the modulation order. STR fully fits in 4G/5G standard requirements and its complexity doesn't require a huge computational resources.

关键词： Peak to average power ratio Mathematical model Modulation Complexity theory Limiting 5G mobile communication

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Hardware implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis

Hardware Implementation of Autoregressive Model Estimation U...

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Kajihara, Koichi Izumi, Shintaro Yoshida, Seiya Yano, Yuji Kawaguchi, Hiroshi Yoshimoto, Masahiko Kobe Univ Grad Sch Syst Informat Kobe Hyogo Japan

ISBN: (纸本)9781538663189

We present a hardware implementation of Burg's method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal can be described by a finite linear aggregate of the previous values. The AR model can be used for spectral analysis as an alternative to the Fourier transform. This approach is a parametric method, and it can yield higher resolutions than nonparametric methods in cases when the signal length is short. Although Burg's method requires a large computational capacity, especially with higher model orders, a fast Burg's method has been proposed for improving this draw back. In this study, we evaluate the influence of the order and the data length of Burg's method on the computational capacity. The hardware implementation method of the fast Burg's method including a two-stage pipeline architecture and a parallelization technique for autocorrelation calculations is proposed. The proposed method is implemented using Verilog HDL and its energy consumption is estimated with the 65-nm CMOS process. The evaluation result shows that the proposed method achieves an energy consumption of 21.6-361.4 nJ for the spectral estimation with a data length of 128-2048 points when the model order is 5.

关键词： AR model Burg's method hardware implementation parametric method spectral analysis

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HARDWARE ARCHITECTURE design OF FRAME RATE UP-CONVERSION FOR HIGH DEFINITION VIDEOS WITH GLOBAL MOTION ESTIMATION AND COMPENSATION

HARDWARE ARCHITECTURE DESIGN OF FRAME RATE UP-CONVERSION FOR...

引用

ieee workshop on signal processing systems (sips)

作者： Hsu, Kung-Yen Chien, Shao-Yi Natl Taiwan Univ Media IC Syst Grad Inst Elect Engn BL 4211Sec 4Roosevelt Rd Taipei 106 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 106 Taiwan

ISBN: (纸本)9781457719219

Frame rate up-conversion (FRUC) with motion compensated interpolation (MCI) is a key operation for motion blur reduction on liquid crystal displays, and dedicated hardware engine design is necessary. In this paper, a hardware architecture for real-time FRUC applications is designed with global motion estimation and compensation. With the concept of motion estimation in low resolution and motion compensation in high resolution, and redesigning several memory bandwidth-hungry modules, a previous work, global-to-local iterative MCI, is modified for hardware design with similar subjective performance. Next, a high-throughput global motion estimation (GME) engine is designed with subsampling technique and parallel hardware architecture, and global motion compensated interpolation and moving block classifier are both designed by sharing the hardware with GME. Moreover, a motion estimation engine is also designed to support various local motion estimation algorithms in different stages. implementation results show that the proposed GME engine can achieve much higher specifications with limited hardware cost increase. Furthermore, the proposed FRUC design can generate 60 1920x1080 interpolated frames per second with the gate count of 1.3M and on-chip memory size of 99kb.

关键词： Frame rate up-conversion (FRUC) motion compensated interpolation (MCI) global motion estimation global-to-local motion blur hardware architecture

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Approximate Comparator: design and Analysis

Approximate Comparator: Design and Analysis

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Zhou, Yangcan Lin, Jun Wang, Jichen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Jiangsu Peoples R China

ISBN: (纸本)9781538663189

As a new design paradigm, approximate computing techniques have drawn tremendous attentions from the very large scale integration (VLSI) design society in recent years. Approximate computing can significantly reduce the energy consumption and the area occupancy at the cost of sacrificing a little performance for some error-tolerant applications. In this paper, an area-efficient, low-power, and high-speed approximate comparator is proposed. Motivated by the existing work, the digits of the input numbers are divided into multiple sub-blocks to perform the comparison in a parallel way to reduce the critical path delay. While in each sub-block, an approach which is different from the existing work is exploit to perform the comparison. Numerical analysis shows that the proposed approximate comparator has a lower error rate than the prior approximate comparator, which is demonstrated by the extensive simulations. When implemented under the Taiwan Semiconductor Manufacturing Company (TSMC) 90nm technology, the implementation results show that the proposed approximate comparator is more efficient than the prior approximate comparator in terms of many basic and compound metrics, such as area, delay, power, and energy-delay-error rate product (EDERP).

关键词： Adders Erbium Very large scale integration Error analysis Approximate computing Delays Multiplexing

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Packet transmission policies for battery operated communication systems

Packet transmission policies for battery operated communicat...

引用

ieee workshop on signal processing systems design and implementation

作者： Li, Y Chakrabarti, C Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

ISBN: (纸本)0780385047

In this paper, we address the problem of designing battery-friendly packet transmission policies for wireless data transmission. Our objective is to maximize the lifetime of battery for wireless devices subject to certain delay constraints. We present three packet transmission schemes and evaluate them with respect to battery performance. The first scheme based on combining multiple packets, utilizes the battery charge recovery due to long idle periods. The second scheme based on a modified version of lazy packet scheduling, draws lower current and is battery efficient. The third scheme which is based on a combination of the above two schemes, has superior battery performance at the expense of larger average packet delay. All three schemes were simulated for a wireless communication framework with internet traffic, and the results validated.

关键词： Telecommunication systems

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Proceedings of the 1998 ieee workshop on signal processing systems, sips

Proceedings of the 1998 IEEE Workshop on Signal Processing S...

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Proceedings of the 1998 ieee workshop on signal processing systems, sips

The proceedings contains 60 papers from the 1998 ieee workshop on signal processing systems (sips 98) - design and implementation. Topics discussed include: cache systems in video signal processing;real time software video encoders;system-on-a-chip design of low-power smart vision systems;hierarchical watermarking techniques;hand-held multimedia terminals;high resolution digital image acquisition using wavelet image compression;enhanced template matching algorithms;filter banks;discrete time-frequency distribution;multichannel reverberation for computer music applications;scheduling strategies for low-energy programmable digital-serial Reed-Solomon codecs;and digital demodulator matching.

关键词： Digital signal processing

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Efficient parallelized particle filter design on CUDA

Efficient parallelized particle filter design on CUDA

引用

workshop on signal processing systems

作者： Chao, Min-An Chu, Chu-Yuan Chao, Chih-Hao Wu, An-Yeu Graduate Institute of Electronics Engineering National Taiwan University Taipei City 10617 Taiwan

ISBN: (纸本)9781424489336

Particle filtering is widely used in numerous nonlinear applications which require reconfigurability, fast prototyping, and online parallel signal processing. The emerging computing platform, CUDA, may be regarded as the most appealing platform for such implementation. However, there are not yet literatures exploring how to utilize CUDA for particle filters. This parer aims to provide two design techniques, A) finite-redraw importance-maximizing (FRIM) prior editing and B) localized resampling, for efficient implementation of particle filters on CUDA, which can be verified to reduce global operations and provide significant speedup. The modifications on algorithm and architectural mapping are evaluated with conceptual and quantitative analysis. From the classic bearings-only tracking experiments, the proposed design is 5.73 times faster than the direct implementation on GeForce 9400m. ©2010 ieee.

关键词： Program processors

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Optimal downlink power-control design methodology for a mobile radio DS-CDMA system 16

Optimal downlink power-control design methodology for a mobi...

引用

ieee workshop on signal processing systems (sips 02)

作者： Tung, TL Yao, K Univ Calif Los Angeles Elect Engn Dept Los Angeles CA 90095 USA

ISBN: (纸本)0780375874

A designed methodology for a downlink power-control technique that maximizes the user-capacity of a DS-CDMA cellular system is proposed. First, the downlink beamforming weights for the base-station antenna-array are designed based on the maximum SIR criterion. Then by optimizing the downlink power-control algorithm subject to a fixed total transmit power constraint, we further increase the SINR at the mobile terminal, thus increasing the capacity of the system. Due to the quasi-convex property of the SINR expression, we formulate the power optimization process as a feasibility problem with linear constraints, which can be solved efficiently by linear programming methods. With the same methodology, we can also minimize the required transmit power while satisfying the SINR threshold constraints. Computer simulations are given to evaluate the optimized downlink capacity, received SINR, and the required transmit power of a DS-CDMA system using antenna-arrays at the base-station.

关键词： Computer simulation Constraint optimization design methodology Downlink Land mobile radio Linear programming Multiaccess communication Receiving antennas signal to noise ratio Transmitting antennas

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A novel MDCT/IMDCT computing kernel design

A novel MDCT/IMDCT computing kernel design

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sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Hwang, Yin-Tsung Lai, Shin-Chi Department of Electrical Engineering National Chung-Hsing University Taichung 402 Taiwan Department of Electronic Engineering National Yunlin University of Science and Technology Touliu Yunlin 640 Taiwan

ISBN: (纸本)0780393341

This paper presents a novel MDCT/IMDCT algorithm and its hardware design. In algorithm derivation, the MDCT/IMDCT computation is first converted into a form of matrix multiplication consisting of a half size DCT-IV kernel and a projection matrix. The DCT-IV kernel is then realized by a fast DCT-II computing scheme. Since MDCT and IMDCT algorithms use the same DCT kernel, a unified architecture using the same set of twiddle factors can be employed for both computations. Based on the proposed algorithm, a novel design mapping is developed with emphasis on the reduction of hardware and memory access complexities. By careful scheduling in computation and memory access schemes, only single port memory modules are needed in lieu of expensive dual port memories. Performance analyses reveal that, given the comparable hardware resource allocation, the proposed design can outperform other MDCT/IMDCT designs in terms of memory storage size, computing latency and fixed point implementation error. © 2005 ieee.

关键词： Computational methods

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