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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

共 1150 条记录，以下是281-290 订阅

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Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling

Parallel Wavelet-based Bayesian Compressive Sensing based on...

引用

ieee International workshop on signal processing systems (ieee sips)

作者： Zhou, Jian Chakrabarti, Chaitali Arizona State Univ SECEE Tempe AZ 85287 USA

ISBN: (纸本)9781538663189

Bayesian compressive sensing (BCS) helps address ill-posed signal recovery problems using the Bayesian estimation framework. Gibbs sampling is a technique used in Bayesian estimation that iteratively draws samples from conditional posterior distributions. However, Gibbs sampling is inherently sequential and existing parallel implementations focus on reducing the communication between computing units at the cost of increase in recovery error. In this work, we propose a two-stage parallel coefficient update scheme for wavelet-based Bayesian compressive sensing, where the first stage approximates the real distributions of the wavelet coefficients and the second stage computes the final estimate of the coefficients. While in the first stage the parallel computing units share information with each other, in the second stage, the parallel units work independently. We propose a new coefficient update scheme that updates coefficients in both stages based on data generated a few rounds ago. Such a scheme helps in relaxing the timing constraints for communication in the first stage and computations in the second stage. We design the corresponding parallel architecture and synthesize it in 7 nm technology node. We show that in a system with 8 computing units, our method helps reduce the execution time by 17.4x compared to a sequential implementation without any increase in the signal recovery error.

关键词： Gibbs sampling parallel implementation Bayesian compressive sensing

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design and implementation of a Highly Accurate Stochastic Spiking Neural Network

Design and Implementation of a Highly Accurate Stochastic Sp...

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35th ieee workshop on signal processing systems (ieee sips)

作者： Tang, Chengcheng Han, Jie Univ Alberta Dept Elect & Comp Engn Edmonton AB Canada

ISBN: (纸本)9781665401449

The emergence of spiking neural networks (SNNs) provide a promising approach to the energy efficient design of artificial neural networks (ANNs). The rate encoded computation in SNNs utilizes the number of spikes in a time window to encode the intensity of a signal, in a similar way to the information encoding in stochastic computing. Inspired by this similarity, this paper presents a hardware design of stochastic SNNs that attains a high accuracy. A design framework is elaborated for the input, hidden and output layers. This design takes advantage of a priority encoder to convert the spikes between layers of neurons into index-based signals and uses the cumulative distribution function of the signals for spike train generation. Thus, it mitigates the problem of a relatively low information density and reduces the usage of hardware resources in SNNs. This design is implemented in field programmable gate arrays (FPGAs) and its performance is evaluated on the MNIST image recognition dataset. Hardware costs are evaluated for different sizes of hidden layers in the stochastic SNNs and the recognition accuracy is obtained using different lengths of stochastic sequences. The results show that this stochastic SNN framework achieves a higher accuracy compared to other SNN designs and a comparable accuracy as their ANN counterparts. Hence, the proposed SNN design can be an effective alternative to achieving high accuracy in hardware constrained applications.

关键词： Field programmable gate arrays (FPGAs) priority encoder stochastic computing spiking neural networks

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VLSI architecture of a MPEG-4 visual renderer

VLSI architecture of a MPEG-4 visual renderer

引用

ieee workshop on signal processing, systems design and implementation (sips 01)

作者： Nguyen-Phuc, QL Sorolla, CM Philips Res France PRF F-92156 Suresnes France

ISBN: (纸本)0780371453

This paper presents the architecture of a hardware block supporting the real time rendering of all 2D natural or synthetic visual objects proposed by the MPEG-4 standard as well as sprite decoding. It is compliant to Main Profile, Level3 and Hybrid Visual Profile. A software model allows to validate the visual quality of the rendered scene. The complexity of this architecture is evaluated and the architectural choices are validated by means of simulations of a behavioral model.

关键词： Video signal processing

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Polynomial Approximation with Non-Uniform Segmentation for Bivariate Functions 34

Polynomial Approximation with Non-Uniform Segmentation for B...

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34th ieee workshop on signal processing systems (sips)

作者： Percelay, Mathieu Bonnot, Justine Arrestier, Florian Menard, Daniel Univ Rennes INSA Rennes CNRS IETRUMR 6164 F-35000 Rennes France

ISBN: (纸本)9781728180991

Embedded applications use more and more sophisticated computations. These computations can integrate the composition of elementary functions which have to be approximated. In the context of scientific computation, mathematical libraries are available but are inefficient for real-time embedded applications. In this context, the efficient evaluation of a complex function requires to design a specific source code or HW block dedicated to this function and the considered input range. Different solutions have been proposed for univariate functions. These techniques are based on iterative methods, look-up tables, bi-/multi-partite table methods or polynomial approximation. Significantly fewer methods are available for multivariate functions. In this paper, we propose a polynomial approximation for software implementation of bivariate-functions. A smart non-uniform segmentation is proposed to better fit irregularities of the approximated function. Furthermore, for best performances, the degree of the bivariate approximating polynomial is dynamic which avoids data and time waste. The experiment results underline the ability of the proposed approach to explore the trade-off between the memory footprint and execution time of the function evaluation.

关键词： Approximate computing Mathematical function approximation Minimum Mean Square Error Method Non-uniform Segmentation Software implementation

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High-speed pipelined ECC processor on FPGA

High-speed pipelined ECC processor on FPGA

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ieee workshop on signal processing systems design and implementation

作者： Chelton, William Benaissa, Mohammed Univ Sheffield Dept Elect & Elect Engn Mappin St Sheffield S1 3JD S Yorkshire England

ISBN: (纸本)9781424403820

This paper details the design of a new high-speed pipelined elliptic curve cryptography (ECC) application specific instruction set processor (ASIP) using field programmable gate array (FPGA) technology. A six-stage pipeline has been applied to the design, and pipeline stalls are avoided via instruction reordering and data forwarding. Three complex instructions are introduced to reduce the latency by reducing the overall number of instructions. The new processor shows improvements over previously reported designs in terms of throughput, latency and area. The higher clock frequencies and low latencies lead to the fastest point multiplication time reported in the literature. An FPGA implementation over GF(2(163)) is shown, which achieves a point multiplication time of 36.77 microseconds at 77.01 MHz on a Xilinx Virtex-E device- over 50% faster than the best figure previously reported.

关键词： Integrated circuit design

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design and implementation of A Convex-Optimized Positioning System on Wireless RF/FPGA Platform

Design and Implementation of A Convex-Optimized Positioning ...

引用

ieee workshop on signal processing systems (sips)

作者： Huang, Li-Hong Shr, Kai-Ting Lin, Ming-Hung Huang, Yuan-Hao Natl Tsing Hua Univ Inst Commun Engn Hsinchu 30013 Taiwan Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan

ISBN: (纸本)9781479965885

This paper presents the design and implementation of a positioning system based on particle filters and a convex optimization processor. The positioning system uses a virtual base-station transform (VBST) and convex optimization algorithm to deal with the none-light-of-sight (NLOS) problem in wireless communication systems. This study designs a modified resampling particle filter to reduce the processing latency with little performance loss. The proposed system uses four modified particle filters to adopt RSS signals from at most four base stations to estimate their distances to the mobile station. Then, the estimated distances are delivered to a convex optimization processor with the VBST algorithm to locate the mobile station. This work implemented the positioning algorithm on Xilinx Virtex-4 FPGA and RF modules to verify the positioning performance. The measurement and analysis results show that the proposed convex-optimized positioning system reduces 20% RMSE in the mixed NLOS/LOS environment compared to the sole particle filtering approach.

关键词： Atmospheric measurements Convex functions Field programmable gate arrays Nonlinear optics Particle measurements Shadow mapping Transforms Field programmable gate arrays Shadow mapping Particle measurements atmospheric monitoring Convex function Transform Positioning systems Particle filters Nonlinear optics BASE STATION

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Task-based Execution of Synchronous Dataflow Graphs for Scalable Multicore Computing

Task-based Execution of Synchronous Dataflow Graphs for Scal...

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ieee International workshop on signal processing systems (sips)

作者： Georgakarakos, Georgios Kanur, Sudeep Lilius, Johan Desnos, Karol Abo Akad Univ Fac Sci & Engn Turku Finland UBL CNRS UMR 6164 INSA Rennes IETR 20 Av Buttes Coesmes F-35708 Rennes France

ISBN: (纸本)9781538604465

Dataflow models of computation have early on been acknowledged as an attractive methodology to describe parallel algorithms, hence they have become highly relevant for programming in the current multicore processor era. While several frameworks provide tools to create dataflow descriptions of algorithms, generating parallel code for programmable processors is still sub-optimal due to the scheduling overheads and the semantics gap when expressing parallelism with conventional programming languages featuring threads. In this paper we propose an optimization of the parallel code generation process by combining dataflow and task programming models. We develop a task-based code generator for PREESM, a dataflow-based prototyping framework, in order to deploy algorithms described as synchronous dataflow graphs on multicore platforms. Experimental performance comparison of our task generated code against typical thread-based code shows that our approach removes significant scheduling and synchronization overheads while maintaining similar (and occasionally improving) application throughput.

关键词： Multicore processing Programming Runtime Synchronization Processor scheduling Generators

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High-performance and energy-efficient heterogeneous subword parallel instructions

High-performance and energy-efficient heterogeneous subword ...

引用

ieee workshop on signal processing systems

作者： Kim, J Wills, DS Georgia Inst Technol Microelect Res Ctr Atlanta GA 30332 USA

ISBN: (纸本)0780377958

High instruction throughput and energy efficiency are becoming increasingly important design requirements for embedded and mobile computing systems. This paper presents the Quantized Color Pack eXtension (QCPX) ISA to improve execution performance of multimedia processing applications on programmable superscalar processors while reducing the energy consumption for these applications. QCPX exploits parallelism within the color space representation (YCbCr: luminance-chrominance) in addition to generic subword parallelism exploited by existing multimedia instruction set extensions (e.g., MMX, SSE, MDMX). We evaluate the performance (execution time in cycles) and energy consumption using QCPX on a media benchmark suite that includes vector median filter, scalar median filter, edge detection, and vector quantization. Our experiment results indicate that a 32-bit QCPX version achieves speedups ranging from 205% to 562% compared with that of a 32-bit baseline RISC version and 90% to 100% over the 32-bit MDMX-like version on identically configured, dynamically scheduled ILP superscalar processors. In addition, the QCPX version reduces the energy consumption from 69% to 83% over the baseline version and 47% to 50% over the MDMX-like version due to the significant reduction of executed instructions and cache accesses.

关键词： Color Computer aided instruction Embedded computing Energy consumption Energy efficiency Filters Instruction sets Mobile computing Parallel processing Throughput

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Increasing the power efficiency of application specific instruction set processors using datapath optimization

Increasing the power efficiency of application specific inst...

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ieee Annual workshop on signal processing systems: design and implementation

作者： Glökler, T Bitterlich, S Meyr, H Aachen Univ Technol Inst Integrated Signal Proc Syst Aachen Germany

ISBN: (纸本)0780364880

Application specific instruction set processors (Asips) can be optimized both for speed and power taking advantage of the flexibility of a synthesized semi-custom implementation. The current case study evaluates the effect of datapath and instruction set optimization using two examples from terrestrial digital video broadcasting (DVB-T) acquisition and tracking algorithms. Starting from a conventional, unoptimized instruction set architecture, which uses simple instructions like any commercially available DSP, incremental application specific optimizations are performed. Results in terms of cycle count and energy per task are used to evaluate the feasibility and the power efficiency of each implementation. The results show a huge potential (> 6x) concerning power savings using this design methodology.

关键词： Digital signal processing

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HIGH-THROUGHPUT DUAL-MODE SINGLE/DOUBLE BINARY MAP PROCESSOR design FOR WIRELESS WAN

HIGH-THROUGHPUT DUAL-MODE SINGLE/DOUBLE BINARY MAP PROCESSOR...

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ieee workshop on signal processing systems

作者： Chen, Chun-Yu Lin, Cheng-Hung (Andy) Wu, An-Yeu Natl Taiwan Univ Grad Inst Elect Engn Taipei 106 Taiwan

ISBN: (纸本)9781424429233

In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm(2) dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mu m CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.

关键词： hardware accelerators turbo codes maximum a-posteriori probability

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