This paper addresses a new kind of security vulnerable spots introduced by Network-on-chip (NoC) use in System-on-Chip (SoC) design. This study is based on the experience of a CAD framework for NoC design and proposes...
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ISBN:
(纸本)0780393333
This paper addresses a new kind of security vulnerable spots introduced by Network-on-chip (NoC) use in System-on-Chip (SoC) design. This study is based on the experience of a CAD framework for NoC design and proposes a classification of weaknesses with regard to usual routing and interface techniques. Finally design strategies are proposed and a new path routing technique (SCP) is introduced with the aim to enforce security.
Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter...
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ISBN:
(纸本)0780393333
Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.
The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation meth...
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ISBN:
(纸本)0780393333
The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation methods are used to achieve the high throughput at relatively low cost of hardware resources. The architecture is verified in simulations and synthesized for ASIC and FPGA technologies. implementation results for FPGA Stratix II devices show that it can work at 120 MHz and process about 40 million samples per second in the regular lossless mode.
In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. ...
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ISBN:
(纸本)0780393333
In this paper, a novel architecture for the implementation of Serial Parallel Multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput because it requires small number of zeros to start a new multiplication cycle at a moderate hardware expense and achieves significant hardware reduction compared to the Double Precision SPM. The proposed technique permits the optimization of the area time product.
The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtain...
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ISBN:
(纸本)0780393333
The purpose of this work is to show the importance of an adequate generation of the excitation signal for the performance of bandwidth extension algorithms for speech signals. Two previously proposed methods of obtaining the excitation signal are analyzed and, based on this analysis, a new method is proposed. The influence of each method in the quality of the reconstructed wideband speech signal is evaluated by quantitative parameters of speech quality.
This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimiz...
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ISBN:
(纸本)0780393333
This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimization approaches are combined to achieve a low-cost interpolation implementation. The proposed interpolation scheme, which produces identical results with the reference software, requires no multiplications and 16-bit integer arithmetic is sufficient for the computation. The instruction set extensions result in cycle savings without much increasing the hardware cost. They also enable in-place processing in the half-pixel interpolation. When the optimizations are applied, it is possible to implement the H.264/AVC decoder without a multiplier.
The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO dec...
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ISBN:
(纸本)0780393333
The authors present a low power and area efficient turbo soft-input soft-output (SISO) decoder based on two-step soft-output Viterbi algorithm (SOVA) targeting wireless mobile communication systems. Our turbo SISO decoder is based on trace back algorithm (TBA) and saves area and power by replacing the FIFO memory with an additional transition metric unit (TMU). The paper presents the implementation of SOVA decoder for constraint lengths K=3, 4, and 5, describing the design methodology and evaluation environment. Simulation results are provided showing up to 20% power saving and 46% area saving compared to a conventional SOVA decoder implementation.
In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication techniqu...
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ISBN:
(纸本)0780393333
In this paper, we describe a novel algorithm for modular exponentiation of large integers and present its hardware implementation. This algorithm combines elements from Montgomery's modular multiplication technique, carry-save and carry-delayed number representations. The major advantage of this algorithm over previously reported algorithms is that it does not require the result of each modular multiplication in the exponentiation process to be converted from the redundant representation back to a nonredundant form. In our algorithm, the conversion is only necessary at the end of all the modular multiplications. Avoiding the conversion speeds up the modular exponentiation process. In addition, the algorithm allows for a fast, modular, and scalable hardware implementation.
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise ...
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ISBN:
(纸本)0780393333
A new class of compander systems is proposed that combines conventional broad-band companders with adaptive filtering based on linear prediction. This allows not only non reduction, but also spectral shaping of noise induced e.g. in FM radio links. Evaluation using a simulation application shows a significant increase in perceived audio quality compared to conventional compander systems.
In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where appli...
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ISBN:
(纸本)0780393333
In this paper we present an automatic design generation methodology for heterogeneous architectures composed of processors, DSPs and FPGAs. This methodology is based on an Adequation Algorithm Architecture where application is represented by a control data flow graph and architecture by an architecture graph. We focus on how to take into account specificities of partially reconfigurable components during the adequation process and for the design generation. We present a method which generates automatically the design for both fixed and partially reconfigurable parts of a FPGA. This method uses prefetching technic to minimize reconfiguration latency of runtime reconfiguration and buffer merging to minimize memory requirements of the generated design.
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