Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines auto...
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ISBN:
(纸本)0780393333
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines automatically whether or not there are any faces in given images and, if so, returns the location and extent of each face. Next, FADECS uses neural network-based classifiers which allow the classification of several facial expressions from features that we develop and describe.
The Koetter-Vardy algorithm is an algebraic soft-decision decoding algorithm for Reed-Solomon codes. Software implementations of the Koetter-Vardy algorithm are considered as part of a redecoding architecture that aug...
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ISBN:
(纸本)0780393333
The Koetter-Vardy algorithm is an algebraic soft-decision decoding algorithm for Reed-Solomon codes. Software implementations of the Koetter-Vardy algorithm are considered as part of a redecoding architecture that augments a hardware hard-decision decoder with soft-decision decoding software on an embedded processor. In this paper we investigate the implementation of the interpolation step of the Koetter-Vardy algorithm on SIMD processor architectures. A parallelization of the algorithm is given using the K'th order Horner's rule for parallel polynomial evaluation. The SIMD algorithm has a running time 2.5 to 4 times faster than a serial implementation on a DSP processor. To gain further speedup we propose a merged-SIMD architecture that calculates the Hasse derivative in parallel with the polynomial updates.
Presented in this paper is a low-complexity iris identification architecture built upon an enhanced periodicity transform, referred to as the prime subspace periodicity transform (PSPT). The proposed PSPT achieves eff...
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ISBN:
(纸本)0780393333
Presented in this paper is a low-complexity iris identification architecture built upon an enhanced periodicity transform, referred to as the prime subspace periodicity transform (PSPT). The proposed PSPT achieves efficient computation by partitioning periodic subspaces into hierarchical prime subspaces. Data decomposition at prime subspaces can be implemented in a simple manner by exploiting the redundancy in correlation computation. The proposed PSPT establishes a theoretical foundation for our work in developing integrated biometric systems for identity authentication. A PSPT-based iris identification architecture is developed that achieves 32.1%-56.2% reduction in computational complexity. Experimental results demonstrate an efficient solution for reliable and accurate iris identification. The proposed PSPT algorithm in combination with architecture optimizations address the challenges in single-chip implementation of biometric systems.
In this paper, we give a detailed presentation of a robust algorithm for detecting arcs of ellipse in a binary image. The characterization of such arcs of ellipse enables the identification between some video image el...
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ISBN:
(纸本)0780393333
In this paper, we give a detailed presentation of a robust algorithm for detecting arcs of ellipse in a binary image. The characterization of such arcs of ellipse enables the identification between some video image elements and the corresponding landmarks in a 3D model of the scene to be represented. This algorithm is based on a classical ellipse property that enables its parameters separation. It provides interesting results even in noisy images or when these arcs are small and partially hidden.
An improved intermediate frequency (IF) architecture for software defined radios is presented. This architecture is programmable, reconfigurable and suited to hardware implementation. The architecture is based on a co...
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ISBN:
(纸本)0780393333
An improved intermediate frequency (IF) architecture for software defined radios is presented. This architecture is programmable, reconfigurable and suited to hardware implementation. The architecture is based on a computationally efficient method of extracting multiple channels belonging to two different communication standards, GSM and IS-95. The core of the system comprises of polyphase DFT filterbanks and very economical fractional rate-change filters. A flexible and efficient sample rate conversion method is also proposed that performs common rate changes using a shared hardware structure. Computational and hardware complexity comparisons are made based on results from a simulation test-bed developed for the proposed system.
This paper presents a functional model based on a hierarchical architecture template meeting with Software Defined Radio System requirements (SDR systems). The concepts and mechanisms required to design future reconfi...
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ISBN:
(纸本)0780393333
This paper presents a functional model based on a hierarchical architecture template meeting with Software Defined Radio System requirements (SDR systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD Uplink, GSM Uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of an heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing...
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ISBN:
(纸本)0780393333
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M.1225, Detection Probability, False Alarm, Missing Probabifity, and Mean Acquisition Time of the proposed timing synchronization scheme are compared with the existing method of 141 to demonstrate the excellence of the proposed scheme. MSE (Mean Square Error) and signal constellation to show the performance of carrier frequency offset estimation is also addressed in this paper.
We studied the efficient implementation of a motion estimation algorithm for H.264/AVC on TMS 320C64x, a VLIW (Very Long Instruction Word) SIMD (Single Instruction Multiple Data) digital signal processor. H.264 motion...
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ISBN:
(纸本)0780393333
We studied the efficient implementation of a motion estimation algorithm for H.264/AVC on TMS 320C64x, a VLIW (Very Long Instruction Word) SIMD (Single Instruction Multiple Data) digital signal processor. H.264 motion estimation algorithms demand much arithmetic operations especially because of the variable block size optimization. The SAD (Sum of Absolute Difference) reuse method is chosen not only to reduce the computation but also to utilize the regular algorithmic structure, which is essential for efficient implementation in parallel and pipelined processors. We applied a few techniques, such as loop length increase for efficient software pipelining, multiblock SAD computation for reducing memory access overhead, block processing for cache miss minimization, and improved quarter-pixel processing. The implementation results show that a real-time implementation of Me for D1 size (720*480) video is possible using a 720MHz TMS320C6416 digital signal processor.
The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communicatio...
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ISBN:
(纸本)0780393333
The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communication system. A multiuser steepest Wiener LMS (MS-WLMS) like structure algorithm along with smoothing/prediction filters to improve tracking quality is suggested. This paper presents a customized and fixed-point hardware parallel implementation of he proposed algorithm for WCDMA uplink transmission in third generation (3G) wireless system. Additional speedup in the execution time is achieved over the well known Maximum Likelihood channel estimation for DS-CDMA. It is also shown that our solution could achieve the real-time requirements of 3GPP standards applied in WCDMA systems.
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the through...
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ISBN:
(纸本)0780393333
Algorithm transformations for increased throughput and decreased power consumption in design of digit-serial FIR filters are discussed in this paper. Pipelining has been used for a long time for increasing the throughput of sequential algorithms. Here we introduce algorithm unfolding, which traditionally has been used in implementation of recursive algorithms, in a sequential FIR algorithm. Pipelining at algorithm and logic level, and algorithm unfolding are compared by HSPICE simulations of netlists extracted from layouts. For a given throughput requirement, the simulations show that algorithm unfolding without any pipelining is preferable for low power operation. Algorithm unfolding yields a decrease of the power consumption with 40, and 50 percent compared to pipelining at the logic or algorithm level, respectively. For minimum power consumption the digit-size should be tuned with the throughput requirement, i.e., using a large digit-size for low throughput requirement and decrease the digit-size with increasing throughput.
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