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Capacity of block transmission systems with quantized inputs and outputs

Capacity of block transmission systems with quantized inputs...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Ndili, O Ogunfunmi, T Santa Clara Univ Dept Elect Engn Santa Clara CA 95053 USA

ISBN: (纸本)0780393333

A common inaccuracy that is made when computing the capacity of digital channels, is to assume that the inputs and outputs of the channel are analog Gaussian random variables and then based upon that assumption, invoke the Shannon capacity bound for an additive white Gaussian noise (AWGN) channel. In a channel utilizing a finite set of inputs and outputs, clearly the inputs and outputs are not Gaussian distributed and Shannon bound is not exact. In this paper we study the capacity of a block transmission AWGN channel with quantized inputs and outputs given the simultaneous constraints that the channel is frequency selective and there exists an average power constraint P at the transmitter. The channel is assumed known at the transmitter. In [13] we show supporting simulation results consequent upon the theoretical framework developed in this paper as well as the results obtained by applying the framework to a practical example.

关键词： Channel capacity

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Energy detection UWB receiver design using a multi-resolution VHDL-AMS description

Energy detection UWB receiver design using a multi-resolutio...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Crepaldi, M Casu, MR Graziano, M Politecn Torino Dipartimento Elettron CERCOM Turin Italy

ISBN: (纸本)0780393333

Ultra Wide Band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VRDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VRDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations.

关键词： Radio systems

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On the way to an H.264 HW/SW reference model: A SystemC modeling strategy to integrate selected IP-blocks with the H.264 software reference model

On the way to an H.264 HW/SW reference model: A SystemC mode...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Amer, I Sayed, M Badawy, W Jullien, G ATIPS Calgary AB T2N 1N4 Canada

ISBN: (纸本)0780393333

SystemC is a new hardware design concept that enables the designer to perform early functional verification of developed hardware blocks by facilitating their integration with software in a unified platform. It provides hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. In this paper, we propose a strategy that enables us to emulate a model of a full HW/SW H.264 encoder. The latest reference software is modified by allowing selected computationally extensive modules to be optionally executed in emulated hardware. SystemC is used for hardware modeling. The proposed strategy enables us to perform early functional verification and conformance analysis of the IP-blocks at the system level of abstraction.

关键词： Product design

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Radix-differential 2D FIR filters

Radix-differential 2D FIR filters

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Aggoun, A Electronic and Electrical Engineering Department De Montfort University Gateway Leicestershire UK

ISBN: (纸本)0780338065

An approach to the realisation of 2D FIR filters based on a novel radix-differential arithmetic is introduced. The differential algorithm is accomplished by coding the input video signal more efficiently using a DPCM coding system. Whereas the filter's coefficients are fed in digit serial fashion and specified using radix-2(n) arithmetic. The proposed approach provides a spectrum of architectures to allow a more flexible design trade off analysis between throughput rate and hardware cost.

关键词： Finite impulse response filter Digital filters signal processing Image coding Throughput Hardware Costs Phase change materials Digital arithmetic Filtering

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A low power VLSI design paradigm for iterative decoders

A low power VLSI design paradigm for iterative decoders

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Elassal, M Baker, A Bayoumi, M Univ Louisana Ctr Adv Comp Studies Lafayette LA 70504 USA

ISBN: (纸本)0780393333

In this paper we present low power Maximum A Posteriori (MAP) decoder architectures using dual supply voltages. The architecture leverages an Application Specific Integrated Circuits (ASIC) structure, where the architecture components that require a higher performance are powered from a high supply voltage V-ddH, and the less demanding components are powered from a low supply voltageV dd Salient features of this architecture include: (a) high level of parallelism, (b) reduced power consumption without affecting the architecture performance, and (c) a tradeoff between the decoding time delay and the number of state metric banks, branch metric banks, and state metric update kernels respectively. The power consumption reduction of the dual-supply voltage over the single-supply voltage has been estimated and the memory access frequencies as well. The proposed architecture achieves approximate 35-40% power reduction from the single-supply architecture.

关键词： VLSI circuits

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implementation of complex-arithmetic heterodyne filter

Implementation of complex-arithmetic heterodyne filter

引用

ieee workshop on signal processing systems

作者： Soderstrand, MA Azam, A Sasidaran, D Nelson, KE Univ Calif Davis Davis CA 95616 USA

ISBN: (纸本)0780377958

Heterodyne filters provide both tunable and adaptive filters with applications in narrow-band interference attenuation for spread-spectrum and other broad-band communications systems. A new complex-arithmetic version of the tunable heterodyne filter offers significant hardware savings over previous versions and can more easily be implemented in adaptive filter applications.

关键词： Adaptive filters Attenuation Band pass filters Frequency Hardware Interference Narrowband signal processing Spread spectrum communication Tunable circuits and devices

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Efficient design of symbol detector for MIMO-OFDM based wireless LANs

Efficient design of symbol detector for MIMO-OFDM based wire...

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Seungpyo, Noh Yunho, Jung Jaeseok, Kim Dept. of Electrical and Electronic Engineering Yonsei University Seoul 120-749 Korea Republic of

ISBN: (纸本)0780393341

In this paper, an efficient hardware architecture for MEMO-OFDM symbol detector with two transmit and two receive antennas is proposed. The proposed symbol detector supports two MEMO-OFDM modes of SFBC-OFDM and SDM-OFDM. It can be implemented with shared-architecture, since the detection algorithms of two MIMO-OFDM modes are similar. Therefore, by eliminating duplicated function blocks, reduced-complexity implementation can be possible. It was designed in a hardware description language and synthesized to gate-level circuits using 0.18um CMOS standard cell library. The total logic gate count for the symbol detector is 164K. By the efficient hardware architecture, the proposed symbol detector results in the reduction of the logic gates by 34% and the power consumption by 38%. © 2005 ieee.

关键词： Local area networks

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Using sliding concentric windows for license plate segmentation and processing

Using sliding concentric windows for license plate segmentat...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Anagnostopoulos, C Anagnostopoulos, I Tsekouras, G Kouzas, G Loumos, V Kayafas, E Univ Aegean Cultural Technol & Commun Dept Mitilini Lesvos Greece

ISBN: (纸本)0780393333

In this paper, a new algorithm for vehicle license plate identification is proposed, on the basis of a novel adaptive image segmentation technique (Sliding Windows) in conjunction with a character recognition Neural Network. The algorithm was tested with 2820 natural scene gray level vehicle images of different backgrounds and ambient illumination. The camera focused on the plate, while the angle of view and the distance from the vehicle varied according to the experimental setup. The, license plates properly segmented were 2719 over 2820 input images (96.4%). The Optical Character Recognition (OCR) system is a two layer Probabilistic Neural Network with topology 108-180-36, whose performance reached 97.4%. The PNN was trained to identify multi-font alphanumeric characters from car license plates based on data obtained from algorithmic image processing.

关键词： Image segmentation

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Efficient motion vector refinement architecture for sub-pixel motion estimation systems

Efficient motion vector refinement architecture for sub-pixe...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Dias, T Roma, N Sousa, L INESC DEETC ISEL ID Lisbon Portugal

ISBN: (纸本)0780393333

This paper proposes a new, scalable and efficient VLSI architecture for real-time sub-pixel motion estimation. The proposed structure is optimized for search strategies using small search ranges, such as hierarchical or sub-pel refinement algorithms. Based on the proposed architecture, a highly modular and configurable motion estimation co-processor capable of estimating optimal motion vectors with any given accuracy and using any known interpolation algorithm is presented. The performance of this processing structure was evaluated by embedding it in a two-level motion estimation system with minimum memory bandwidth requirements, that estimates half-pixel accurate motion vectors using a two-step search procedure. Experimental results for implementations on ASIC and FPGA devices show that by using the proposed architecture it is possible to estimate motion vectors up to the 4CIF image format, in real-time with any given sub-pixel accuracy.

关键词： Motion estimation

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Battery-friendly design of signal processing algorithms

Battery-friendly design of signal processing algorithms

引用

ieee workshop on signal processing systems

作者： Raghavan, P Chakrabarti, C Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

ISBN: (纸本)0780377958

Portable systems today are designed with lowering the energy consumption as the primary design metric. This is unfortunate since maximizing battery lifetime is. a more appropriate metric, and lowering energy does not necessarily mean improving battery lifetime. In this paper we first show how to design battery-friendly implementations of common signal processing kernels such as FIR filters and FFT. The basic idea is to generate a load profile that results in better battery behavior. Next, we demonstrate how frequency scaling can be used effectively to improve the battery behavior of an application such as MPEG2.

关键词： Algorithm design and analysis Batteries Energy consumption Finite impulse response filter Frequency Kernel Process design signal design signal processing algorithms Voltage

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