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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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Hough transform algorithm for FPGA implementation

Hough transform algorithm for FPGA implementation

引用

ieee Annual workshop on signal processing systems: design and implementation

作者： Tagzout, S Achour, K Djekoune, O Ctr Dev Technol Avancees Microelect Lab Algiers 16075 Algeria

ISBN: (纸本)0780364880

In this paper a novel algorithm for computing the Dough Transform (HT) is introduced. The basic idea consists in using a combination of an incremental method with the usual HT expression to join circuit performances and accuracy requirements. The algorithm is primarily developed to fit Field Programmable Gate Arrays (FPGA) implementation that have become a competitive alternative for high performance Digital signal processing applications. The induced architecture presents a high degree of regularity, making its VLSI implementation very straight forward. This implementation may be achieved by generator program, assuring a shorter design cycle and a lower cost. For illustration, implementation results of an HT parameter extractor for 8-bit image pixels is given.

关键词： Field programmable gate arrays

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Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing

Area-efficient 2-D shift-variant convolvers for FPGA-based d...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Cardells-Tormo, F Molinet, PL Digital ASIC Technol Grp R&D Large Format Technol Lab Sant Cugat Del Valles 08147 Spain

ISBN: (纸本)0780393333

Two dimensional (2-D) convolutions are local by nature;hence every pixel in the output image is computed using surrounding information, i.e. a moving window of pixels. Although the operation is simple, the hardware is conditioned by the fact that due to bandwidth efficiency full raster rows must be read from the external memory, and that a row-major image scan should be performed to support shift-variant convolutions. When extending the architectures developed in prior art to support shift-variant convolutions, we realize that they require large amounts of on-chip memory. While this fact may not have a large cost increase in ASIC implementations, it makes FPGA implementations expensive or not feasible. In this paper, we propose several novel FPGA-efficient architectures for generating a moving window over a row-wise print path. Because the proposed concepts have different throughput and resource utilization, we provide a criteria to choose the optimum one for any design point.

关键词： Image processing

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High-radix cordic algorithms for VLSI signal processing

High-radix cordic algorithms for VLSI signal processing

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Aoki, T Nogi, H Higuchi, T Tohoku Univ Sendai Japan

ISBN: (纸本)0780338065

This paper presents high-radix CORDIC algorithms for high-speed sine and cosine computation. Since the CORDIC calculation takes O(n) steps for evaluating a function in n-bit precision, significant reduction of processing latency is required for real-time signal processing applications. In this paper, we present a unified approach to low-latency CORDIC implementation based on high-radix algorithms, and propose ''radix-2-4-8 CORDIC processor'', which achieves low-latency computation by changing radix during execution.

关键词： Digital signal processing

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Reliable low-power multimedia communication systems

Reliable low-power multimedia communication systems

引用

ieee workshop on signal processing, systems design and implementation (sips 01)

作者： Shanbhag, NR Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA

ISBN: (纸本)0780371453

The topic of designing reliable and energy-efficiency multimedia systems in deep submicron technologies is addressed. First, various sources of noise and other non-idealities in current and future semiconductor technologies are described. Following this, two distinct design philosophies for implementing reliable and energy-efficient multimedia communication domains are presented. Both approaches optimize across algorithmic, architectural and circuit domains.

关键词： Multimedia systems

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signal processing in CMOS image sensors

Signal processing in CMOS image sensors

引用

ieee Annual workshop on signal processing systems: design and implementation

作者： Nair, R Raj, K Intel Corp Microproc Res Lab Santa Clara CA 95051 USA

ISBN: (纸本)0780364880

A CMOS Image Sensor codenamed EYE2 developed on a standard Intel CMOS process and designed into the Intel 971 Camera Kit is described. EYE2 converted incident visual images into 10-bit digital data streams for still and video imaging applications. The analog signal processing essential to achieving the very high SNR desired is detailed. A fully differential architecture was implemented In order to achieve a desired SNR of 60dB with known techniques [1]...[6] for the minimization of signal degradation. Novel techniques implemented helped speedup the analog signal path and reduce power consumption in the chip.

关键词： signal processing

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Low-complexity time-domain channel estimators for mobile wireless OFDM systems

Low-complexity time-domain channel estimators for mobile wir...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Werner, S Enescu, M Koivunen, V Aalto Univ Signal Proc Lab SMARAD CoE FIN-02015 Helsinki Finland

ISBN: (纸本)0780393333

This paper proposes low-complexity time-domain channel estimators for OFDM systems. Time-domain channel estimation combined with frequency domain equalization is an attractive approach, since it can provide lower complexity and better estimator performance than pure frequency domain processing. In the particular case of constant modulus (M-PSK) modulation, we show that the transmission matrix is unitary. Therefore, the simple correlator channel estimator turns out to be optimal. For the case of non-constant envelope the transmission matrix is not unitary anymore, but its corresponding correlation matrix is strongly diagonal. Therefore, a low-complexity approximate LS solution is proposed which avoids matrix inversion. A study of decision-feedback errors is performed, which suggest that iterative re-decoding of the data further improves the channel estimates. Simulations carried out for a wide range of mobile speeds demonstrate that the proposed estimators, using only 2% of pilot data, outperform recently proposed [41 time- and frequency-domain approaches.

关键词： Mobile telecommunication systems

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Image analysis and partitioning for FPGA implementation of image restoration

Image analysis and partitioning for FPGA implementation of i...

引用

ieee Annual workshop on signal processing systems: design and implementation

作者： Ogrenci, S Bazargan, K Sarrafzadeh, M Northwestern Univ Dept Elect & Comp Engn Evanston IL 60637 USA

ISBN: (纸本)0780364880

In the center of our work lies an FPGA implementation of an iterative image restoration algorithm. Our work presents an initial analysis of the algorithm as well as modifications made on the algorithm during the adaptation onto reconfigurable platform. We are presenting our hardware design for the image restoration algorithm and our estimations on the performance of the FPGA implementation. Our results show that the speedup gained for practical systems varies between 6.5 and 10.2 for different images. In this paper we are also proposing and evaluating a statistical method for analysis of images subject to restoration to gain insight into the convergence time of the restoration algorithm. Based on this we explored a image partitioning strategy using this statistical analysis.

关键词： Field programmable gate arrays

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design and implementation of a FPGA sigma-delta Power DAC

Design and implementation of a FPGA sigma-delta Power DAC

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Magrath, AJ Clark, IG Sandler, MB King's Coll London London United Kingdom

ISBN: (纸本)0780338065

In this paper we discuss the design and implementation of a FPGA Power DAC for digital audio applications. The paper concentrates on the sigma-delta modulator, which is used to convert an oversampled PCM input signal into a 1-bit code suitable for controlling a power switch. The design of the bit-flipping architecture used to reduce the pulse-repetition frequency of the output is discussed, together with the the loop filter structure and transfer function design. This is followed by details of FPGA architecture and the optimisations required for implementation.

关键词： Digital to analog conversion

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Fast rate allocation schemes for JPEG2000

Fast rate allocation schemes for JPEG2000

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Wu, ZZ Zheng, NN Xi An Jiao Tong Univ Inst Artificial Intelligence & Robots Xian Peoples R China

ISBN: (纸本)0780393333

JPEG2000 can provide excellent rate-distortion performance. However, the conventional post compression rate- distortion (PCRD) optimum algorithm in JPEG2000 is not enough efficient for IC design. Calculation and storage of the rate-distortion slope and search of the optimum truncation points are complexity and they require a large quantity of memory. In this paper, two schemes are proposed to reduce computation and memory for the real-time rate allocation in JPEG2000. A simplification scheme is used to facilitate calculation of the rate-distortion slopes based on some approximate treatments by means of logarithm expression. The other scheme can find all the truncation points for every code-block through a round search based on the 256 quality layers which are divided in parallel with tier1-coding. Compared with PCRD, PSNR of reconstructed images using our schemes decrease very slightly which can be omitted in most applications.

关键词： Transform coding Rate-distortion Discrete wavelet transforms Artificial intelligence Intelligent robots Decoding Algorithm design and analysis PSNR Image reconstruction Application software

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Error analysis methods for the fixed-point implementation of linear systems

Error analysis methods for the fixed-point implementation of...

引用

ieee International workshop on signal processing systems (sips)

作者： Hilaire, Thibault Volkova, Anastasia UPMC Univ Paris 06 Sorbonne Univ LIP6 UMR 7606 F-75005 Paris France

ISBN: (纸本)9781538604465

In this paper we propose to perform a complete error analysis of a fixed-point implementation of any linear system described by data-flow graph. The system is translated to a matrix-based internal representation that is used to determine the analytical errors-to-output relationship. The error induced by the finite precision arithmetic (for each sum-of-product) of the implementation propagates through the system and perturbs the output. The output error is then analysed with three different point of view: classical statistical approach (errors modeled as noises), worst-case approach (errors modeled as intervals) and probability density function. These three approaches allow determining the output error due to the finite precision with respect to its probability to occur and give the designer a complete output error analysis. Finally, our methodology is illustrated with numerical examples.

关键词： Quantization (signal) Linear systems Roundoff errors Lattices Probability density function

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