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检索条件"任意字段=SiPS 2005: IEEE Workshop on Signal Processing Systems - Design and Implementation"

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design of low error fixed-width squarer

Design of low error fixed-width squarer

引用

ieee workshop on signal processing systems

作者： Cho, KJ Kim, WK Kim, BK Chung, JG Chonbuk Natl Univ Dept Elect & Informat Engn Chonju South Korea

ISBN: (纸本)0780377958

This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation.

关键词： design methodology Digital signal processing Encoding Equalizers Error compensation Error correction Frequency domain analysis Image coding Pattern recognition Vector quantization

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implementation of a wireless multimedia DSP chip for mobile applications

Implementation of a wireless multimedia DSP chip for mobile ...

引用

ieee workshop on signal processing systems

作者： Heo, KL Sunwoo, MH Oh, SK Ajou Univ Sch Elect & Comp Engn Suwon 442749 South Korea

ISBN: (纸本)0780377958

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perforin four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 mum HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.

关键词： Circuit testing Clocks Digital signal processing chips Frequency synchronization Hardware design languages Libraries Mobile communication Parallel processing Timing Viterbi algorithm

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System integration issues for set-top box

System integration issues for set-top box

引用

1997 ieee workshop on signal processing systems (sips 97) - design and implementation

作者： Gass, WK Texas Instruments Inc Dallas United States

ISBN: (纸本)0780338065

In a cost sensitive consumer electronics market, the most cost-efficient implementation of the digital satellite set-top box is required in order to be competitive. The system functionality and the implementation rational of the set-top box is described. Tradeoffs regarding hardware vs. software implementation are examined. Examples of how the system design affects the size and bandwidth of the memory requirements are given. Although the current generation of processors are capable of implementing real-time video decoding, they still are not a cost-effective solution for the digital set-top box.

关键词： Satellite communication systems

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implementation of DCT-domain motion estimation and compensation

Implementation of DCT-domain motion estimation and compensat...

引用

1998 ieee workshop on signal processing systems - design and implementation (sips'98)

作者： Kleihorst, R Cabrera, F Philips Res Labs Digital VLSI Grp Eindhoven Netherlands

ISBN: (纸本)0780349970

Hybrid video compression schemes store an entire image for predictive coding. Traditionally, this image is stored in the time domain needing almost 5 Mbit of memory for main-level image format. The amount of storage space can be reduced if the data is stored in the RLE-DCT domain, even using the available compression and buffer-control algorithm to guarantee a storage amount. We show that a hardware implementation is feasible and worthwhile in relation to traditional encoders. Motion estimation is performed by recursive blockmatching, at sub-pixel accuracy.

关键词： Image compression

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design approaches for MPEG engines for broadband and mobile applications 16

Design approaches for MPEG engines for broadband and mobile ...

引用

ieee workshop on signal processing systems (sips 02)

作者： Kuroda, I Nishitani, T NEC Corp Ltd Kawasaki Kanagawa Japan

ISBN: (纸本)0780375874

This paper is going to present recent advances in MPEG-2/-4 audio and video (AV) codec implementations for broadband and mobile applications. Several design approaches based on special purpose hardwired LSIs, programmable DSPs, media processors, embedded MPUs, and MPUs for personal computes(PCs), which are used to implement MPEG engines are introduced. Then, design approaches for low power and low cost AV codec LSIs for broadband and mobile applications are discussed, by introducing recent implementation examples. Finally, future trends and challenges are discussed.

关键词： Codecs Decoding Digital signal processing Engines Hardware Microprocessors MPEG 4 Standard MPEG standards Transform coding Video compression

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design of a DVB-S receiver in FPGA

Design of a DVB-S receiver in FPGA

引用

ieee workshop on signal processing systems

作者： Cardells-Tormo, F Pérez-Pascual, A Torres-Carot, V Valls-Coquillat, J Almenar-Terrè, V Hewlett Packard Corp ICD R&D Lab Barcelona 08190 Spain

ISBN: (纸本)0780377958

This paper deals with the design of an all-digital receiver for the DVB-S standard in FPGA. We describe the implementation issues of the next stages: digital acquisition at intermediate frequency, downconversion to baseband, synchronization in time, and synchronization in frequency and phase. The high data rates needed by this all-digital architecture can only be achieved by a latest generation FPGA and with a careful design of each subsystem. So, for each stage we propose the most efficient design for Xilinx FPGAs in terms of area and throughput. And, finally, we present the implementation results of a complete DVB-S digital receiver on a Virtex-II Pro FPGA.

关键词： Bandwidth Clocks Data acquisition Digital video broadcasting Field programmable gate arrays Frequency synchronization Sampling methods Satellite broadcasting Throughput Transponders

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An EMFi-film sensor based ballistocardiographic chair:: Performance and cycle extraction method

An EMFi-film sensor based ballistocardiographic chair:: Perf...

引用

ieee workshop on signal processing systems design and implementations (sips 05)

作者： Junnila, S Akhbardeh, A Värri, A Koivistoinen, T Tampere Univ Technol Inst Signal Proc FIN-33101 Tampere Finland

ISBN: (纸本)0780393333

New sensor technologies open possibilities for measuring traditional biosignals in new innovative ways. This, together with the development of signal processing systems and their computing power, can sometimes give new life to old measurement techniques. Ballistocardiogram is one such technique, originally promising but quickly replaced by the now very popular electrocardiogram. A ballistocardiograph chair, designed to look like a normal office chair, was built and fitted with pressure sensitive EMFi-films. The films are connected via a charge amplifier to a medical bioamplifier. The system was accepted for medical use in Tampere University Hospital and patient measurements have been performed. The system is presented and it's performance evaluated. A wireless version of the system is needed to hide the cabling from the user. This will make the chair indistinguishable from a normal office chair. Overview of first wireless prototype is given. To analyze recorded BCG, individual BCG cycles must be extracted from the signal containing respiration and movement artifacts. A method for this and results of it's application are presented. The developed system can be used for BCG measurements and it is able to automatically extract individual BCG cycles, but it has some limitations which are presented in the paper.

关键词： Biosensors

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Power and Thermal Modeling for Communication systems

Power and Thermal Modeling for Communication Systems

引用

ieee International workshop on signal processing systems (sips)

作者： Wolf, Marilyn Bhattacharyya, Shuvra Florence, Jacques Sapio, Adrian E. Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

ISBN: (纸本)9781509033614

Power and thermal characteristics have emerged as first-order design goals for all types of semiconductors, including embedded signal and information processing systems. This paper surveys the basic physical principles of power and thermal behavior and argues that statistical models, such as Markov decision processes, are well-suited to the management of power and thermal behavior at both design time and run time.

关键词： communication systems power consumption thermal behavior VLSI

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Optimized software synthesis for digital signal processing algorithms: An evolutionary approach

Optimized software synthesis for digital signal processing a...

引用

1998 ieee workshop on signal processing systems - design and implementation (sips'98)

作者： Teich, J Zitzler, E Bhattacharyya, SS Swiss Fed Inst Technol Inst TIK CH-8092 Zurich Switzerland

ISBN: (纸本)0780349970

Based on the model of synchronous data flow (SDF) [13], so called single appearance schedules are known to provide memory-optimal schedules. Among these, the problem of buffer memory optimization is treated: (I) An Evolutionary Algorithm (EA) is applied to efficiently explore the (in general) exponential search space of actor firing orders. (2) For each order, the buffer costs are evaluated by applying a dynamic programming post-optimization step (GDPPO).

关键词： Digital signal processing

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Analysis and implementation of uniform quadrature bandpass sampling

Analysis and implementation of uniform quadrature bandpass s...

引用

sips 2005: ieee workshop on signal processing systems - design and implementation

作者： Sun, Yi-Ran Signell, Svante Stockholm Sweden

ISBN: (纸本)0780393341

Sampling noise folding causes a large SNR degradation at the output of BandPass Sampling (BPS) system. A sampling architecture based on Generalized Quadrature Band-Pass Sampling (GQBPS) was proposed in [1]. Theoretical analysis showed that such architecture is promising to reduce the SNR degradation due to noise aliasing. In this paper, Uniform Quadrature BandPass Sampling (UQBPS) as a special case of GQBPS is analyzed for both ideal sampling and a sample-and-hold. One available implementation method to UQBPS is shown and discussed at the circuit level. © 2005 ieee.

关键词： Bandpass filters

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