In recent mobile communication systems, impairments in analog circuits cannot be disregarded owing to the need to achieve high performance. Errors in analog circuits consist of a distortion of a power amplifier(PA), g...
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In recent mobile communication systems, impairments in analog circuits cannot be disregarded owing to the need to achieve high performance. Errors in analog circuits consist of a distortion of a power amplifier(PA), gain and phase imbalance in a quadrature modulator(QMOD) and a quadrature demodulator(QDEMOD), dc offset, frequency offset, and so on. Because of high accuracy of compensation, many techniques of error compensation by using digital signalprocessing have been studied recently. Digital predistorter(DPD), which can eliminate odd-order distortion caused by PA nonlinearity, is one of the compensation techniques. However, in the case that direct conversion architecture is used in a loop-back path, errors in a QMOD and a QDEMOD affect the performance of DPD. Previously, we proposed an error estimation technique for a QMOD and a QDEMDO by using a variable phase shifter and evaluated the performance through computer simulation. In this paper, we evaluate the performance through an experiment by image rejection ratio(IRR) and error vector magnitude(EVM) in the case that the output of a QMOD is directly connected to the input of a QDEMOD. The results show that IRR improvement after compensation is 10 dB at the output of the QMOD and EVM improvement after compensation is 10 dB at the output of the QMOD and 20 dB at the output of the QDEMOD.
To satisfy the increasing demand for extremely tight overlay accuracy in semiconductor manufacturing processes, all the measurement error factors in alignment systems and overlay measurement tools need be identified a...
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To satisfy the increasing demand for extremely tight overlay accuracy in semiconductor manufacturing processes, all the measurement error factors in alignment systems and overlay measurement tools need be identified and eliminated. The principle of most alignment systems is based on imageprocessing of target marks on the wafer under bright-field illumination. Although the phenomenon that the sensitivity to the alignment error varies with the step height (SH) of the mark has been known and used for evaluating the performance of the alignment optics, no investigation has been made into the origin and the physical mechanism of the phenomenon. We propose a simplified optical model that can account for the origin of the asymmetric image and clarify its relation to the SHs. The model is validated with simulation and experimental results. The improved performance of an alignment system using marks with optimally designed SHs is demonstrated. (C) 2007 Optical Society of America.
A mesoscopic-level method for clarifying living cell dynamics is described that uses Monte Carlo simulation of biological molecule interactions. The molecules are described as particles that take a random walk in 3-di...
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In this paper, we propose a multiprocessor DSP simulation toolkit suitable for performanceevaluation of data-parallel applications like voice processing. The proposed toolkit uses the benefits of multi-level parallel...
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ISBN:
(纸本)9781424418534
In this paper, we propose a multiprocessor DSP simulation toolkit suitable for performanceevaluation of data-parallel applications like voice processing. The proposed toolkit uses the benefits of multi-level parallelism and clustering. Different DSP clusters are considered for the multiprocessor DSP simulation engine in which the DSP processors are grouped to cooperate. Satisfying the communication requirements, two global and local communication engines (GCE and LCE) implement the real behavior of intra- and inter-cluster communications. Using efficient abstraction levels for interconnections reduces the simulation time significantly. Abstract communication modeling, cycle-accurate behavior, and mull-level controlling are the most important features of the proposed simulation platform. performance of the simulator is verified by standard single- and mull-channel voice processing applications such as ITU-T G.729a speech codec.
In CT, PET/CT and SPECT/CT imaging research, we are often involved in the design, development and evaluation of instrumentation, data acquisition methods, and image reconstruction and processing techniques. Ideally, c...
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In CT, PET/CT and SPECT/CT imaging research, we are often involved in the design, development and evaluation of instrumentation, data acquisition methods, and image reconstruction and processing techniques. Ideally, clinical trials using patient images from actual imaging systems should be used in the evaluation studies. In practice, clinical trials are difficult to perform due to the difficulties and the high costs in acquiring ‘good quality’ clinical images and physicians' time to read them. Most importantly, there is a lack of known ‘truth’ in most clinical images. In the past, although computer simulation methods allowed generation of a large number of images with known ‘truth’, they suffered from the availability of computer generated phantoms that realistically model human anatomy and physiological functions and the ability to generate simulate data that accurately represent data acquired from actual medical imaging systems. We have developed a 4D computer generated phantom that are based on the Visible Human data and cardiac and respiratory gated MRI and CT data from normal human subjects. The non-uniform rational b-splines (NURB) computer graphics tools were used to allow accurate modeling of the shapes of 3D anatomical structures and generation of collections of phantoms that represent variations in anatomical structures and physiological functions found in different patient populations. Also, analytical and Monte Carlo simulation methods have been developed to provide data that accurately model the imaging system geometry, and photon interactions in the phantom and within the imaging system. Applications of the simulation tools to CT, PET/CT and SPECT/CT imaging research will be demonstrated with sample research projects. They demonstrate the potential utility of the simulation tools in a wide variety of applications in the research and development of instrumentation, image reconstruction and processing methods of different medical imaging modalities in th
This paper presents a modular coprocessor architecture for embedded real-time image and video signalprocessing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coproce...
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ISBN:
(纸本)9783540736226
This paper presents a modular coprocessor architecture for embedded real-time image and video signalprocessing. Applications are separated into high-level and low-level algorithms and mapped onto a RISC and a coprocessor, respectively. The coprocessor comprises an optimized system bus, different application specific processing elements and I/O interfaces. For low volume production or prototyping, the architecture can be mapped onto FPGAs, which allows flexible extension or adaption of the architecture. Depending on the complexity of the coprocessor data paths, frequencies up to 150 MHz have been achieved on a Virtex II-Pro FPGA. Compared to a RISC processor, the performance gain for an SSD algorithm is more than factor 70.
To analyze common topologies of communication systems there are several probabilistic analysis strategies existing. Regarding the analysis of the influence of routing strategies probabilistic assumption is hard to val...
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ISBN:
(纸本)9789077381366
To analyze common topologies of communication systems there are several probabilistic analysis strategies existing. Regarding the analysis of the influence of routing strategies probabilistic assumption is hard to validate. We used a discrete event simulation based analysis method to examine the influence of routing strategies within communication structures using a ring topology. By modeling the routing strategy in detail we are able to easily determine a realistic performance behavior under different load conditions.
The computational demand of signalprocessing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But to be able to take advantage of the b...
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ISBN:
(纸本)9783540736226
The computational demand of signalprocessing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But to be able to take advantage of the benefits of these systems, new strategies are required how to map applications to such a system and how to evaluate the system's performance at a very early design stage. We will present a static, analytical, bottom-up methodology for temporal and spatial mapping of applications to MP-SoCs based on packing. Furthermore we will demonstrate how the result can be used for performanceevaluation and system improvement without the need for simulations.
Evaluating different architectures is an important step in implementing signalprocessing algorithms in hardware. Often specific resource or memory requirements and performance can be estimated only through simulation...
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ISBN:
(纸本)9781424412211
Evaluating different architectures is an important step in implementing signalprocessing algorithms in hardware. Often specific resource or memory requirements and performance can be estimated only through simulation. This can be difficult when detailed system descriptions are used. There is a need for quick simulation and estimation of performance. The Rapid Abstract Control (RAC) model is presented as an approach to solve this problem. Simple primitives are defined that can be used to construct models for simulation. The Single Scale Retinex (SSR) algorithm is used to demonstrate the effectiveness of the modeling approach.
To overcome the drawbacks of the Mobile IPv6 protocol on handling local mobility management, IETF proposed the HMIPv6 protocol which introduces an intermediate mobility anchor point (MAP) to hide the movement of a mob...
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ISBN:
(纸本)9781424418534
To overcome the drawbacks of the Mobile IPv6 protocol on handling local mobility management, IETF proposed the HMIPv6 protocol which introduces an intermediate mobility anchor point (MAP) to hide the movement of a mobile node within a local area. However, the MAP forms a bottleneck in the network since all the traffic destined for its served nodes has to go through it Most research on HMIPv6 focuses on protocol optimisation, and performance analysis of HMIPv6 is usually simulation-based. In this paper, we employ a performanceevaluation formalism named PEPA to investigate the performance tradeoffs of MAPS in HMIPv6. performance measures such as response time and MAP utilisation are presented.
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