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8th southern programmable logic conference, SPL 2012

作者： Moreno, Juan Pablo Redlich, Rodolfo Carvajal, Gonzalo Figueroa, Miguel Department of Electrical Engineering University of Concepción Concepción Chile

ISBN: (纸本)9781467301862

This paper presents a compact and low-power digital implementation of the Roughness Index, which provides an estimate of the fixed-pattern noise present in an infrared video stream. This noise is caused by imperfections in the fabrication of the focal plane array and its readout circuitry, in addition to other time-variant processes. The index is continuously used during normal operation of the imager to activate calibration mechanisms that compensate for these limitations. Our FPGA-based prototype computes the Roughness Index on infrared video at 30fps and a resolution of 720x480 pixels. On a low-cost Xilinx Spartan 3E XC3S500 FPGA, adding our circuit to an existing system increases logic resource utilization by only 6% and power consumption by 1.59 mW. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Hazard-free implementation of the extended burst-mode asynchronous controllers in look-uptable based FPGA

Hazard-free implementation of the extended burst-mode asynch...

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4th southern conference on programmable logic

作者： Oliveira, Duarte L. Sato, Sandro S. Saotome, Osamu de Carvalho, Ricardo T. Inst Technol Aeronaut Div Engn Eletron IEE Praca Marechal Eduardo Gomes 50 BR-12228900 Sao Jose Dos Campos Brazil IEAv Div Fis Aplicada EFA BR-12228840 Sao Jose Dos Campos Brazil

ISBN: (纸本)9781424419920

FPGAs have been mainly used for design of synchronous circuits. It is, however, difficult to design asynchronous circuits on them because the circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as extended burst-mode, on FPG, As based on look-up table architectures. We state a sufficient condition so the implementation in FPGAs becomes essential hazard-free. By doing that, asynchronous circuits, besides their intrinsic advantages over synchronous ones, may also take advantage of integration, lower costs and design short-time associated with FPGA designs.

关键词： Field programmable gate arrays (FPGA)

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A dynamic buffer resize technique for networks-on-chip on FPGA

A dynamic buffer resize technique for networks-on-chip on FP...

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southern conference on programmable logic

作者： Véstias, Mário P. Neto, Horácio C. INESC-ID ISEL IPL Portugal INESC-ID IST UTL Portugal

ISBN: (纸本)9781424488483

Networks-on-chip have a relative area and delay overhead compared to buses. These can be improved in application specific systems where heterogeneous communication infrastructures provide high bandwidth in a localized fashion and reduce underutilized resources. However, for general purpose architectures, design time techniques are not efficient. One approach for improving area and/or performance of NoCs for general purpose systems is to consider dynamic adaptation of the resources at runtime. In this paper, we analyze the buffer resize approaches applied to FPGA and propose a buffer resize technique. The results show that the technique improves the area and the performance of the architecture on FPGA but is less efficient than ASIC implementations. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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PC-BASED programmable MEMORY AND logic DESIGN WORKSTATION.

PC-BASED PROGRAMMABLE MEMORY AND LOGIC DESIGN WORKSTATION.

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Wescon/84 conference Record.

作者： Walters, Stephen M. Valley Data Sciences Mountain View CA USA Valley Data Sciences Mountain View CA USA

The subject of this paper is a new generation of PC-Based programmable Memory and logic Design Workstations. It is shown that the use of personal computers in the implementation of these design support tools maximizes their efficiency and value compared to traditional approaches. A full-featured programmable Memory and logic Design Workstation called the 160 Series is described. The Workstation operates with the IBM PC as its host in a closely-coupled architecture in order to take advantage of the many features of the PC.

关键词： COMPUTER AIDED DESIGN

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Educating Hardware Design - From Boolean Equations to Massively Parallel Computing Systems 9

Educating Hardware Design - From Boolean Equations to Massiv...

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9th southern conference on programmable logic (SPL)

作者： Knodel, Oliver Zabel, Martin Lehmann, Patrick Spallek, Rainer G. Tech Univ Dresden Dept Comp Sci D-01062 Dresden Germany

ISBN: (纸本)9781479968480

The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. In this paper we present lectures and especially practical FPGA design courses for bachelor and master students. We introduce a selection of individual projects, which were realized by students in practical courses. With examples from final bachelor projects and master theses we demonstrate the quality of education and its integration into current research. We describe possible improvements of labs, such as automated test benches and a remote FPGA laboratory for advanced courses.

关键词： Boolean algebra educational courses electronic engineering education embedded systems field programmable gate arrays further education logic design parallel architectures Boolean equations FPGA design courses advanced courses automated test benches bachelor students computer science education quality electrical engineering field-programmable gate arrays final bachelor projects hardware design hardware development high-performance systems integrated circuits massively parallel computing systems massively parallel hardware architecture master students master theses practical courses remote FPGA laboratory Computer architecture Computers Educational institutions Field programmable gate arrays Hardware System-on-chip Field programmable gate arrays computer hardware design Embedded systems Advanced Courses Continuing Education electrical engineering Computer hardware computer science system-on-chip parallel computing system Parallel architectures logic design Computer Architecture Boolean algebra Educational institutions

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Tip-tilt mirror control based on FPGA for an adaptive optics system

Tip-tilt mirror control based on FPGA for an adaptive optics...

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3rd southern conference on programmable logic

作者： Gago, F. Rodriguez-Ramos, L. Herrera, G. Gigante, J. Alonso, A. Viera, T. Piqueras, J. Diaz, J. J. Inst Astrofis Canarias Div Technol C Via Lactea S-N Tenerife 38200 Spain Inst Astrofis Canarias Div Technol E-38200 San Cristobal la Laguna Spain

ISBN: (纸本)9781424406067

This paper describes the development of the tip-tilt mirror control for an adaptive optics system based on the use of FPGA technology instead of using the traditional approach with DSP or microprocessor. The aim of this work is to show that for this kind of application the FPGA technology is not only a viable solution but probably also the best one in some situations, especially when a huge amount of parallel data processing is needed. This will probably be the case of adaptive optics systems for very large telescopes (1). A brief description of the whole adaptive optics system will be given although the paper will focus especially on the tip-tilt mirror control and its implementation with FPGAs. A new version of the deformable mirror control is also being implemented in FPGAs and will be finished in the near future.

关键词： Field programmable gate arrays (FPGA)

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Implementation of a fully pipelined BCD multiplier in FPGA

Implementation of a fully pipelined BCD multiplier in FPGA

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8th southern programmable logic conference, SPL 2012

作者： Guardia, Carlos Eduardo Minchola Digital System Lab. - School of Engineering Universidad Autónoma de Madrid Madrid Spain

ISBN: (纸本)9781467301862

Decimal multiplication is one of the most frequently used operations in financial, scientific, commercial and internet-based applications. This paper presents an efficient implementation of a fully pipelined decimal multiplier designed with Carry Save Addition and coded into a reduced group of BCD-4221. This design is based on multiplier operands recoded in Signed-Digit radix-10, a simplified partial products generator, and decimal adders. A variety of multipliers architectures are processed on a Virtex-6 FPGA device. Several assessments are carried out in various N by M multiplications and their respective synthesis results show slightly optimistic figures in terms of area and delay in regard to some previously published works. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Digital circuit design using FPGAs

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COMPUTERS & INDUSTRIAL ENGINEERING 1996年第1-2期31卷 127-129页

作者： Ali, KS Computer Engineering Technology Department University of Southern Mississippi Hattiesburg MS 39406-5137 USA

Field programmable Gate Arrays are generic devices that contain a vast number of basic digital components. The interconnections between these components are defined by the user. By specifying these interconnections different digital circuits may be realized. FPGAs are reprogrammable devices, making the change from one digital circuit to another as simple as downloading a new interconnection file. Furthermore the definition of the interconnection file may be carried out at high level machine languages, making the design and debugging of complex digital circuits rather simple. This publication discusses the use of FPGA as an alternate solution to ASICs. A review of the FPGA technology and its impact on the use of ASICs is carried out. This is followed by a projection of the impact of FPGA on digital technology. Finally methods on introducing FPGA technology to in the classroom and its impact on the quality of future engineers in considered. A case study of the FPGA impact on the Computer Engineering Technology Department of the University of southern Mississippi will be considered.

关键词： FPGA programmable logic integrated circuits digital circuits

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Automated signature insertion in combinational logic patterns for HDL IP core protection

Automated signature insertion in combinational logic pattern...

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4th southern conference on programmable logic

作者： Castillo, Encarnacion Parrilla, Luis Garcia, Antonio Meyer-Baese, U. Botella, Guillermo Lloris, Antonio Univ Granada Dept Elect & Comp Technol E-18071 Granada Spain Florida State Univ Dept Elect & Comp Engn Tallahassee FL 32306 USA Univ Complutense Madrid Dept Comp Architecture & Automat E-28040 Madrid Spain

ISBN: (纸本)9781424419920

This paper presents significant improvements to previous watermarking technique for Intellectual Property Protection (IPP) of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using resources included within the original system. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting that, in addition to easy the signature hosting, leads to reduced area penalties. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.

关键词： Watermarking

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Design of Solar Inverter Based on CPLD 3

Design of Solar Inverter Based on CPLD

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3rd International conference on Power and Energy Systems Engineering, (CPESE)

作者： Hou, Yi-You Tsai, Hung-Hsiang Wang, Chu-Yi Lee, Kun-Xu Hsiao, Wen-Sheng Southern Taiwan Univ Sci & Technol Dept Elect Engn Tainan Taiwan

In this paper, the design and implementation of complex programmable logic device (CPLD) based solar inverter which generates power of AC 110 volts is proposed. In this framework, the former adopt DC to DC boost convert circuit and the latter adopt bipolar full-bridge inverter, and then complex programmable logic device to control system is used. The system uses four solar photovoltaic modules with connection and then can generate 5080 volt of DC. The former DC to DC boost converter voltage and transfers circuit, we adopt pulse-width modulation (PWM) technology and the voltage feedback control to stabilize voltage at the value of 200 volt. The latter converter adopts bipolar sinusoidal pulse width modulation (SPWM) technology such that power cord arrives to 110 volt of alternating current output. (C) 2016 The Authors. Published by Elsevier Ltd.

关键词： complex programmable logic device (CPLD) DC/DC boost convert pulse width modulation (PWM)

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