The proceedings contain 42 papers. The topics discussed include: an open-source framework for heterogeneous MPSoC Generation;a co-design methodology for processor-centric embedded systems with hardware acceleration us...
ISBN:
(纸本)9781467301862
The proceedings contain 42 papers. The topics discussed include: an open-source framework for heterogeneous MPSoC Generation;a co-design methodology for processor-centric embedded systems with hardware acceleration using FPGA;HardNoC: a platform to validate networks on chip through FPGA prototyping;memory bandwith reduction in video coding systems through context adaptive lossless reference frame compression;real time QHDTV motion estimation architecture design for DMPDS algorithm;hardware-based computation of the roughness index for infrared imagers;a high performance and low memory bandwidth architecture for motion estimation targeting high definition digital videos;memory efficient FPGA implementation of motion and disparity estimation for the multiview video coding;and low cost and high throughput multiplierless design of a 16 point 1-D DCT of the new HEVC video coding standard.
The proceedings contain 35 papers. The topics discussed include: LIBOR market model simulation on an FPGA parallel machine;protection of microprocessor-based cores for FPL devices;FPGA-based smart sensor implementatio...
ISBN:
(纸本)9781424470891
The proceedings contain 35 papers. The topics discussed include: LIBOR market model simulation on an FPGA parallel machine;protection of microprocessor-based cores for FPL devices;FPGA-based smart sensor implementation with precise frequency to digital converter for flow measurement;a genetic programming based approach for efficiently exploring architectural communication design space of MPSOCS;an environment for energy consumption analysis of cache memories in SOC platforms;the development of a hardware abstraction layer generator for system-on-chip functional verification;a placement tool for a NOC-based dynamically reconfigurable system;FPGA based floating-point library for CORDIC algorithms;Montgomery modular multiplication on reconfigurable hardware: fully systolic array vs parallel implementation;decimal division: algorithms and FPGA implementations;and parallel decimal multipliers using binary multipliers.
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of US copyright law for private use of patrons those articles in this volume ...
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of US copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. Copyright (c)2012 by IEEE. IEEE Catalog Number: CFP1221B-ART. ISBN: 978-1-4673-0186-2.
In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmablelogic blocks of arbitrary architectures. We formulate the problem as a graph matching problem a...
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ISBN:
(纸本)9781424438464
In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmablelogic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. This algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.
A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmab...
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ISBN:
(纸本)9781424419920
A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmablelogic cells, 160 programmable 10 Blocks and 16Kbits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mu m logic 1P6M Salicide 1.8V/3.3V process, its die size is 6.1x6.6 mm(2), with the package of QFP208.
This paper proposes an area efficient signal processing architecture to perform Iddt test calibration through vector multiplication. The design follows the Field programmable Array organization, and capitalizes on the...
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ISBN:
(纸本)9781424419920
This paper proposes an area efficient signal processing architecture to perform Iddt test calibration through vector multiplication. The design follows the Field programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300kHz, independently of vector size.
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