A Phase Locked Loop (PLL) based on digital signal processing and random sampling is proposed in this paper. Field programmable Gate Array (FPGA) technology is used to implement a prototype. The random sampling scheme ...
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ISBN:
(纸本)9781424406067
A Phase Locked Loop (PLL) based on digital signal processing and random sampling is proposed in this paper. Field programmable Gate Array (FPGA) technology is used to implement a prototype. The random sampling scheme is used to reduce the sampling frequency requirements without aliasing effects. The possibility of sampling and processing at lower frequencies allows the implementation of complete-digital high-frequency systems, without limitations imposed by the analog to digital converter and the signal processing unit. The basic principles are presented, and the implemented algorithms are described. Experimental results show the PLL performance.
In this paper we present radix r = 2(k) divider for fixed point operands. The divider divides in a radix r = 2(k), producing k bits at each iteration. The proposed digit recurrence algorithm has two different architec...
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ISBN:
(纸本)9781424438464
In this paper we present radix r = 2(k) divider for fixed point operands. The divider divides in a radix r = 2(k), producing k bits at each iteration. The proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one is optimized for configurable logic (FPGAs). Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. Additionally a throughput-latency-area comparison of pipelined and sequential dividers implementation is disclosed.
Traditional genetic algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings ...
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ISBN:
(纸本)9781424419920
Traditional genetic algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The compact genetic algorithm (CGA) is a probability vector based genetic algorithm. The article presents an FPGA implementation of the standard compact genetic algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for implementation, the architecture processing speed and the solving power of the CGA for evolvable hardware.
Low-cost FPGAs have comparable number of Configurable logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. This leads to the difficulty for CAD tools to successfully and optimally...
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ISBN:
(纸本)9781424438464
Low-cost FPGAs have comparable number of Configurable logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. This leads to the difficulty for CAD tools to successfully and optimally map a circuit into these devices. Instead of switching to resource-rich FPGAs, the designers could employ depopulation based clustering technique which underuses CLBs, hence improves routability by spreading the logic over the architecture. However, all depopulation based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven non-uniform depopulation based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. We adjust the capacity of the CLB based on the criticality of the logic block. Paper analyzes the effect of depopulation strategies on area and delay performance. Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28%. More importantly, T-NDPack decreases critical path delay by 2.89%.
There exists several FPGA architectures that can be partially reconfigured at run-time. The advantage of partial run-time reconfiguration is that it allows to develop new algorithmic solutions for many applications. B...
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ISBN:
(纸本)9781424419920
There exists several FPGA architectures that can be partially reconfigured at run-time. The advantage of partial run-time reconfiguration is that it allows to develop new algorithmic solutions for many applications. But a limiting factor for using frequent dynamic reconfiguration could be the reconfiguration overhead. In order to study the potential of frequent run-time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. In this paper, we provide a formal treatment of the reconfiguration costs and compare them for models of standard partially reconfigurable FPGAs and 2-level reconfigurable FPGAs.
This paper presents a low cost FPGA based solution for a real-time moving object tracking system. A specialized architecture is presented based on a soft RISC processor capable of running kernel based mean shift track...
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ISBN:
(纸本)9781424438464
This paper presents a low cost FPGA based solution for a real-time moving object tracking system. A specialized architecture is presented based on a soft RISC processor capable of running kernel based mean shift tracking algorithm. The system includes a frame grabber unit that stores the video frame in DDR RAM using direct memory access, a video display unit to monitor the tracking statistics and a soft processor capable of running mean shift tracking algorithm within the required time constraint.
Dynamic reconfiguration of FPGAs allows the dynamic management of various tasks that describe an application. This new feature permits, for optimization purpose, to place tasks on line in an available region of the FP...
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ISBN:
(纸本)9781424438464
Dynamic reconfiguration of FPGAs allows the dynamic management of various tasks that describe an application. This new feature permits, for optimization purpose, to place tasks on line in an available region of the FPGA. Dynamic reconfiguration of tasks leads to some communication problems since tasks are not present in the matrix during all computation time. This dynamicity needs to be supported by the interconnection network. In this paper, we propose the implementation of a flexible interconnection network supporting such dynamicity. The proposed architecture is fully compliant with the present state-of-art. dynamically reconfigurable circuits such as Xilinx Virtex family of FPGA.
In design of embedded systems for security applications, flexibility and tamper-resistance are two important factors to be considered. High frequency of updates and high costs of ASIC and their long design time urge u...
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ISBN:
(纸本)9781424438464
In design of embedded systems for security applications, flexibility and tamper-resistance are two important factors to be considered. High frequency of updates and high costs of ASIC and their long design time urge us to use a secure FPGA as an alternative. In this paper a secure FPGA is proposed for secure implementation of crypto devices. The FPGA architecture is based on Asynchronous methodology and is resistant against multiple side channel attacks such as Power Attacks and Fault Attacks. AES algorithm implementation shows the native resistance of SCAR-FPGA.
A reconfigurable platform for sensor networks is presented. This platform has features that allow easy reuse of the node in several applications avoiding redesigning the system from scratch. The node includes an FPGA ...
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ISBN:
(纸本)9781424406067
A reconfigurable platform for sensor networks is presented. This platform has features that allow easy reuse of the node in several applications avoiding redesigning the system from scratch. The node includes an FPGA which is the core of the reconfiguration capabilities of the node. Several hardware interfaces for sensor standar protocols like 12C or PWM have been developed and implemented in the FPGA. Remote reconfiguration is an important feature and sensor networks can take advantage of it In order to improve the global performance.
This work presents a modulator implemented in a FPGA for power matrix converters. Its function is to operate as a peripheral unit of a digitally-controlled system in order to generate duty cycles for each of the conve...
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ISBN:
(纸本)9781424406067
This work presents a modulator implemented in a FPGA for power matrix converters. Its function is to operate as a peripheral unit of a digitally-controlled system in order to generate duty cycles for each of the converter switches and provide a safe commutation of the switching devices. The correct generation of duty cycles and sequences was verified, as well as the safe commutation of bi-directional switches. The performance of the modulator in conjunction with the power stage and a DSP, which performs the high level control layer, was also analyzed.
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