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检索条件"任意字段=Southern Conference on Programmable Logic"

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Polynomic curve based representation system implemented using FPGAs

Polynomic curve based representation system implemented usin...

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4th southern conference on programmable logic

作者： Pineiro, Carlos Valbuena, Cristina Mecha, Hortensia Univ Complutense Madrid Comp Architecture Dept E-28040 Madrid Spain

ISBN: (纸本)9781424419920

A polynomic curve based representation system is a three-dimensional system for rendering images using polynomic curves instead of triangles meshes. This system allows render a scene in a way that the computational cost depends on the image size more than on the scene complexity. Moreover, It allows the user to describe a scene using a minimal amount of data in comparison with traditional methods. According to that, we have implemented a hardware that demonstrates how this kind of applications can be accelerated in a huge grade using the proper solution. The hardware was implemented on a FPGA;thanks to it, the execution times were very reduced, showing a very promising speedup compared against an only software solution.

关键词： Field programmable gate arrays (FPGA)

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Exploring FPGA capabilities for building symmetric multiprocessor systems

Exploring FPGA capabilities for building symmetric multiproc...

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3rd southern conference on programmable logic

作者： Huerta, Pablo Castillo, Javier Ignacio Martinez, Jose Pedraza, Cesar Univ Rey Juan Carlos Escuela Super Ciencias Expt & Tecnol C Tulipan S-N Madrid 28933 Spain

ISBN: (纸本)9781424406067

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.

关键词： Field programmable gate arrays (FPGA)

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AxB ≠ BxA in terms of power consumption:: Some examples on FPGA

AxB ≠ BxA in terms of power consumption:: Some examples on ...

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3rd southern conference on programmable logic

作者： Boemo, Eduardo Sutter, Gustavo Univ Autonoma Madrid Escuela Politecn Superior E-28049 Madrid Spain

ISBN: (纸本)9781424406067

This paper shows that, under certain conditions, digital arithmetical circuits do not meet the addition commutation property in terms of power consumption. That is, the power consumed by the operation AxB is different from BxA. As a consequence, it is possible to get a power saving simply permuting the circuit inputs, wherever any of the following three conditions are present: a) The data to be processed has a strong temporal correlation;b) The delays between the circuit paths are highly unequalized;c) One of the input data communication is broadcast type, meanwhile the other is local. In order to verify these hypotheses, several binary multipliers were constructed and measured. The power consumption reduction resulted between 12% and 28% in Virtex FPGAs.

关键词： Field programmable gate arrays (FPGA)

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Fast placement-intact logic perturbation targeting for FPGA performance improvement

Fast placement-intact logic perturbation targeting for FPGA ...

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3rd southern conference on programmable logic

作者： Zhou, Catherine L. Tang, Wai-Chung Wu, Yu-Liang Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China

ISBN: (纸本)9781424406067

This work presents a novel, accurate, and fast post-layout logic perturbation method for improving LUT-based FPGA routing, without affecting the placement. The ATPG-based rewiring techniques are used to design the Rewiring engine, which is embedded into VPR, the most powerful academic FPGA CAD tool currently. Compared with VPR's high-quality results, our method can reduce critical path delay by up to 31.74% (avg. 10%) without disturbing placement or sacrificing area. The CPU time used by the Rewiring engine is only 5% of the total time consumed by VPR's placement and routing. All the benchmark circuits can be placed and routed within 3 minutes, which is much faster than the SPFD approach. This paper also analyzes the power of the ATPG-based rewiring techniques in LUT-based FPGAs. Experimental results show that 3% of all nets can be replaced by their alternative wires for FPGA performance improvement.

关键词： Field programmable gate arrays (FPGA)

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LOW COST, QUICK TURNAROUND, HIGH PERFORMANCE SEMI-CUSTOM SOLUTION: programmable logic.

LOW COST, QUICK TURNAROUND, HIGH PERFORMANCE SEMI-CUSTOM SOL...

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Wescon/84 conference Record.

作者： Vithayathil, Joseph Natl Semiconductor Corp Santa Clara CA USA Natl Semiconductor Corp Santa Clara CA USA

A significant development in the history of semiconductor devices is the invention of programmable logic devices. The intent of this paper is to take a comprehensive look into the world of programmable logic as one of... 详细信息

关键词： logic DEVICES

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Soft error in FPGA-implemented asynchronous circuits

Soft error in FPGA-implemented asynchronous circuits

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southern conference on programmable logic

作者： Kuang, Weidong Bai, Yu Department of Electrical Engineering University of Texas - Pan American 1201 W. University Dr. Edinburg TX 78539 United States

ISBN: (纸本)9781424488483

In this paper, we investigate the mechanism of soft error generation and propagation in asynchronous circuits which are implemented on FPGAs. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed. The results show that it is much easier to detect the soft error in asynchronous circuits implemented on FPGAs so that FPGAs can be reprogrammed, compared with traditional synchronous circuits. © 2011 IEEE.

关键词： Field programmable gate arrays (FPGA)

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POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON FPGA 25

POWER-EFFICIENT RANGE-MATCH-BASED PACKET CLASSIFICATION ON F...

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25th International conference on Field programmable logic and Applications

作者： Qu, Yun R. Prasanna, Viktor K. Univ Southern Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781467381239

Packet classification is a kernel application performed at network routers. Many classification engines are optimized for prefix and exact match, while a range-to-prefix translation can lead to rule set expansion. Under limited power budget, it is challenging to achieve high classification throughput. In this paper, we present a high-performance and power-efficient packet classification engine on FPGA. We construct a modular Processing Element ( PE);each PE compares a stride of the input packet header against a stride of a range boundary. We concatenate multiple PEs into a systolic array. Efficient power optimization techniques including self-enabled power gating and entropy-based scheduling are explored on our architecture. Experimental results show that, for 4 K 15-field rule sets, our prototype on a state-of-the-art FPGA can achieve 250 Million Packets Per Second (MPPS) throughput. Using the proposed power optimization techniques, our classification engine consumes 30 % of the power without sacrificing the throughput.

关键词： packet classification Field programmable gate arrays power budget Energy sources Engines Throughput Power (Psychology)

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FPGA Acceleration of Rotation in Homomorphic Encryption using Dynamic Data Layout 33

FPGA Acceleration of Rotation in Homomorphic Encryption usin...

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33rd International conference on Field-programmable logic and Applications (FPL)

作者： Yang, Yang Long, Weihang Kannan, Rajgopal Prasanna, Viktor K. Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90007 USA Tsinghua Univ Dept Elect Engn Beijing Peoples R China DEVCOM Army Res Lab Los Angeles CA 90094 USA Univ Southern Calif Los Angeles CA USA

ISBN: (纸本)9798350341515

Homomorphic Encryption (HE) is a promising technique to guarantee the security and privacy of Machine Learning (ML) applications in the cloud. Rotation is a key operation in HE ML;however, the high computational complexity and memory bandwidth requirements severely limit its performance. This work proposes a low-latency HE rotation accelerator targeting HBM-enabled FPGAs. First, we identify memory inefficiencies due to the access patterns of various sub-routines in rotation. We propose a dynamic data layout technique that converts large stride memory accesses to unit stride accesses to improve the bandwidth utilization. We leverage this technique to develop an FPGA accelerator that supports rotation for various HE parameter settings. The accelerator utilizes an optimized dataflow and an architecture specially designed to perform the dynamic data layout. We evaluate the accelerator using AMD U280 FPGA. Our design achieves up to 2.1x speedup compared with two commonly used static layout approaches and up to 1.47x speedup compared with state-of-the-art GPU implementation across various rotation benchmarks.

关键词： FPGA acceleration homomorphic encryption rotation parallel computing

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Revisiting Atari 2600 on an FPGA

Revisiting Atari 2600 on an FPGA

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8th southern programmable logic conference, SPL 2012

作者： Flach, Guilherme Conceição, Calebe Johann, Marcelo Reis, Ricardo Instituto de Informática - PPGC/PGMicro Av. Bento Gonçalves 9500 Porto Alegre RS Brazil

ISBN: (纸本)9781467301862

In this work we revisit the Atari 2600, the first widely popular home video game, recreating it on a programmable hardware. The console is designed from the scratch using the Verilog Hardware Description Language (HDL) and prototyped on an FPGA board. The analog television system is replaced by the VGA system without relying on a framebuffer. The project is full featured including joystick controls and audio. © 2012 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Proposal for Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA 9

Proposal for Parallel Fixed Point Implementation of a Radial...

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9th southern conference on programmable logic (SPL)

作者： de Souza, Alisson C. D. Fernandes, Marcelo A. C. Fed Univ Rio Grande Norte UFRN Dept Comp Engn & Automat DCA Natal RN Brazil

ISBN: (纸本)9781479968480

This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate, and interpolation using the sine function, were also analyzed in hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

关键词： field programmable gate arrays interpolation least mean squares methods logic gates radial basis function networks ANN response FPGA LMS algorithm RBF Virtex-6 xc6vcx240t-1ff1156 XOR gate Xilinx artificial neural network field programmable gate array hardware implementation least mean square algorithm nonlinear classification parallel fixed point implementation processing time radial basis function network sine function system generator platform Delays Equations Field programmable gate arrays Mathematical model Neurons Table lookup Vectors Field programmable gate arrays Radial basis function networks Least mean square algorithm exclusive or gate Interpolation Least squares method Table lookup Artificial neural networks processing time logic gates Mathematical Model Fixed point

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