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检索条件"任意字段=Southern Conference on Programmable Logic"

共 560 条记录，以下是61-70 订阅

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MICROPROCESSOR-BASED DEMONSTRATION OF A programmable logic CONTROLLER.

MICROPROCESSOR-BASED DEMONSTRATION OF A PROGRAMMABLE LOGIC C...

引用

conference Proceedings - IEEE Southeastcon '86.

作者： Whitehead, Michael B. Green, David G. Southern Co Services Birmingham AL USA Southern Co Services Birmingham AL USA

The hardware design, and support software for a microprocessor-based programmable logic controller (PLC) are described. This controller implements relay logic using current software-control techniques. The PLC consists of a microcomputer, power interface software, and the software relay control package (SORCON). The controller is programmed over a serial line by either an operator using a CRT terminal or by a computer in a distributed processing demonstration.

关键词： CONTROL EQUIPMENT

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CONCURRENT CALCULATIONS ON RECONFIGURABLE logic DEVICES APPLIED TO THE ANALISYS OF VIDEO IMAGES

CONCURRENT CALCULATIONS ON RECONFIGURABLE LOGIC DEVICES APPL...

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5th southern conference on programmable logic

作者： Geninatti, Sergio R. Benavides Benitez, Jose Ignacio Hernandez Calvino, Manuel Guil Mata, Nicolas Univ Nacl Rosario Fac Ciencias Exactas Ingn & Agrimensura Ave Pellegrini 250 RA-2000 Rosario Argentina Univ Cordoba Escuela Politecn Super Cordoba Spain Univ La Habana Fac Fis Dpto Fis Gen Havana Cuba Univ Malaga Dpto Arquitectura Comp Malaga Spain

ISBN: (纸本)9781424438464

This paper presents the design and implementation on FPGA devices of an algorithm for computing the similarity between neighbor photograms in a video sequence using luminance information. Making use of the well-known flexibility of Reconfigurable logic Devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexation. The experimental work has established a tradeoff between concurrent sequential resources and functional blocks, in order to achieve maximum operation speed with minimum silicon area. In order to evaluate the efficiency of the designed system, we have compared the performance of the hardware solution with that of calculations done via software using general-purpose processors with and without the MMX extension.

关键词： logic devices

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Significant Papers from the First 25 Years of the FPL conference 25

Significant Papers from the First 25 Years of the FPL Confer...

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25th International conference on Field programmable logic and Applications

作者： Leong, Philip H. W. Amano, Hideharu Anderson, Jason Bertels, Koen Cardoso, Joao M. P. Diessel, Oliver Gogniat, Guy Hutton, Mike Lee, JunKyu Luk, Wayne Lysaght, Patrick Platzner, Marco Prasanna, Viktor K. Rissa, Tero Silvano, Cristina So, Hayden Wang, Yu Univ Sydney Sydney NSW 2006 Australia Keio Univ Tokyo 108 Japan Univ Toronto Toronto ON M5S 1A1 Canada Delft Univ Technol NL-2600 AA Delft Netherlands Univ Porto P-4100 Oporto Portugal Univ NSW Kensington NSW Australia Univ South Brittany Lorient France Altera Corp San Jose CA USA Imperial Coll London London England Xilinx Res Labs San Jose CA USA Univ Paderborn Paderborn Germany Univ Southern Calif Los Angeles CA USA Nokia Espoo Finland Politecn Milan Milan Italy Univ Hong Kong Hong Kong Hong Kong Peoples R China Tsinghua Univ Beijing Peoples R China

The list of significant papers from the first 25 years of the Field-programmable logic and Applications conference (FPL) is presented in this paper. These 27 papers represent those which have most strongly influenced ...

ISBN: (纸本)9781467381239

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FPGA-based acceleration of fingerprint minutiae matching

FPGA-based acceleration of fingerprint minutiae matching

引用

3rd southern conference on programmable logic

作者： Lindoso, Almudena Entrena, Litis Izquierdo, Juan Univ Carlos III Madrid Elect Technol Dept Avda Univ 30 E-28911 Madrid Spain

ISBN: (纸本)9781424406067

Nowadays fingerprint is the most widely used and studied biometric technique because of its universality, distinctiveness, and decreasing cost of the sensing devices. Among the fingerprint identification techniques, minutiae-based algorithms are the most mature. However, these methods are computationally expensive, particularly for comparison with large databases. This work is devoted to study the performance gains that can be achieved with the use of FPGAs. To this purpose, two minutia-based fingerprint matching algorithms have been selected and implemented in a FPGA in order to compare the requirements and performance of software and hardware implementations. Experimental results demonstrate the feasibility of implementing fingerprint matching algorithms in current FPGA devices achieving speed-ups of one or two orders of magnitude. Customization of the proposed implementations can lead to several architectures optimized in size, price, speed or accuracy.

关键词： Field programmable gate arrays (FPGA)

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FPGA-based transmit/receive distributed controller for the TR modules of an L band antenna (SAR)

FPGA-based transmit/receive distributed controller for the T...

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4th southern conference on programmable logic

作者： Siman, Javier Jaquenod, Guillermo Mascialino, Hugo DTA SA Monsenor Pablo Cabrera 5020X5008HJP Cordoba Argentina Comis Nacl Actividades Espaciales RA-1063 Buenos Aires DF Argentina

ISBN: (纸本)9781424419920

A Synthetic Aperture Radar (SAR) is built around a physical matrix of independent Transmit & Receive Modules (TRM). Each TRM has several parameters to be controlled to attain optimal performance and to compensate production dispersion and operation drift, and for calibration of the complete TR chain. The SAR is an instrument of the SAOCOM Low Earth Orbit satellite, which will be launched on 2010. It has 105 TRM, organized in 21 tiles, each one containing 5 TRM and a redundant controller. This paper presents the project and implementation of the redundant controller, based around a space qualified antifuse FPGA. This device was chosen after evaluation of SRAM, FLASH and antifuse technologies, and special considerations have been taken to reduce components count, minimize power consumption, cost, weight, and improve reliability.

关键词： Field programmable gate arrays (FPGA)

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Synthesis of Locally-Clocked Asynchronous Systems with Bundled-Data Implementation on FPGAs 9

Synthesis of Locally-Clocked Asynchronous Systems with Bundl...

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9th southern conference on programmable logic (SPL)

作者： Garcia, Kledermon Oliveira, Duarte L. Curtinhas, Tiago d'Amore, Roberto Inst Tecnol Aeronaut ITA SJC Div Engn Eletron Sao Paulo Brazil Inst Aeronaut & Espaco IAE CTA SJC Div Sistemas Aeronaut Sao Paulo Brazil

ISBN: (纸本)9781479968480

This paper presents a method for an optimized synthesis of asynchronous digital systems having an FPGA as target device. The method employs the decomposition design style (data-path + controller) and uses the extended burst-mode specification to describe the controller. Asynchronous system synthesized by the method operates in "two-phase handshake protocol", allowing a better performance. In this method, the decomposition is implemented by bundled-data using components of the synchronous paradigm. This new method proposes to design asynchronous FSM with local clock The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any programmable device, such as CPLDs and FPGAs, without macro-cells' mapping concern A with four benchmarks shows an average performance increase of 21% with an average area increase of 27% LUTs, when compared with synchronous versions.

关键词： asynchronous logic local-clock AFSM XBM speccation bundled-data

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FLEXIBLE CONFIGURATION OF MULTI-CHIP SYSTEM USING ACTEL FPGAs

FLEXIBLE CONFIGURATION OF MULTI-CHIP SYSTEM USING ACTEL FPGA...

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5th southern conference on programmable logic

作者： Guichal, Guillermo Rodriguez, Gaston Koenig, Mauro FRBB UTN Ingn Elect Bahia Blanca Buenos Aires Argentina Emtech Bahia Blanca Buenos Aires Argentina

ISBN: (纸本)9781424438464

Modem embedded systems may consist of many devices, which may have complex interconnections between them. Many of these devices may also need to be configured and programmed during development and production. The JTAG port and boundary scan techniques are the industry standard for that task, but are not supported by all devices. This paper presents the use of an FPGA as the means of interconnection between all devices and to provide a single configuration interface for the system. The flexible interconnections in the FPGA allow for faster development times and flexible and reconfigurable interconnections. The FPGA also provides a single, standard JTAG interface to the user during development and production The FPGA acts as a bridge between the standard programming interface and proprietary programming protocols and interfaces, easing development and simplifying the programming task during production and on the field.

关键词： Field programmable gate arrays (FPGA)

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Design of a field-programmable dual-precision floating-point arithmetic unit

Design of a field-programmable dual-precision floating-point...

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16th International conference on Field programmable logic and Applications

作者： Diniz, Pedro C. Govindu, Gokul USC Inst Informat Sci 4676 Admiralty WaySuite 1001 Marina Del Rey CA 90292 USA Univ Southern Calif Dept Elect Engn Los Angeles CA 90089 USA

ISBN: (纸本)9781424403127

The growth in FPGA capacity and the inclusion of embedded arithmetic cores has enabled the use of these devices for general purpose floating-point computing. Despite their clock rate handicap with respect to contemporary general-purpose processors, these devices can be field-programmable to meet the precision requirements and operator-level parallelism of a specific computation. In this paper we describe and evaluate the performance of dual-precision, pipelined, floating-point arithmetic cores for addition, multiplication and division. Each of these arithmetic cores can be switched at run-time to perform either one double-precision operation, or with the same hardware resources, perform two single-precision operations. We also implemented quad-precision cores which can be switched to perform either one quad-precision operation or two double-precision operations. As an application of these cores, we describe and evaluate the performance potential of a custom, but flexible, vector processing units as part of a system-level architecture targeting a Xilinx Virtex-II Pro (TM) 100 FPGA device connected to multiple SRAM banks.

关键词： Digital arithmetic

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Teaching programmable logic controllers: a hands-on and skill-building approach 7

Teaching programmable logic controllers: a hands-on and skil...

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IEEE 7th International conference on Industrial Cyber-Physical Systems (ICPS)

作者： Hansen, Esper Puggaard de Oliveira Hansson, Svend Koenig, Matthias Univ Southern Denmark Dept Technol & Innovat Sonderborg Denmark

ISBN: (纸本)9798350363029;9798350363012

programmable logic controllers (PLCs) are essential in process automation and production technology. Hence, educating students about PLCs and their usage is crucial to prepare skilled workers in relevant engineering fields. This paper proposes a multidisciplinary teaching approach combining technical and business perspectives in using PLCs. Besides such 'hard skills,' we encourage the students to become creative and learn to collaborate. We describe how our course is structured and how company visits are integrated. A student evaluation of our course is given and discussed. In general, the evaluation supports our approach.

关键词： programmable logic controller education business

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Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform 32

Accelerating Monte-Carlo Tree Search on CPU-FPGA Heterogeneo...

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32nd International conference on Field-programmable logic and Applications (FPL)

作者： Meng, Yuan Kannan, Rajgopal Prasanna, Viktor Univ Southern Calif Los Angeles CA 90007 USA US Army Res Lab Adelphi MD USA

ISBN: (纸本)9781665473903

Monte Carlo Tree Search (MCTS) methods have achieved great success in many Artificial Intelligence (AI) benchmarks. The in-tree operations become a critical performance bottleneck in realizing parallel MCTS on CPUs. In this work, we develop a scalable CPU-FPGA system for Tree-Parallel MCTS. We propose a novel decomposition and mapping of MCTS data structure and computation onto CPU and FPGA to reduce communication and coordination. High scalability of our system is achieved by encapsulating in-tree operations in an SRAM-based FPGA accelerator. To lower the high data access latency and inter-worker synchronization overheads, we develop several hardware optimizations. We show that by using our accelerator, we obtain up to 35x speedup for in-tree operations, and 3x higher overall system throughput. Our CPU-FPGA system also achieves superior scalability wrt number of parallel workers than state-of-the-art parallel MCTS implementations on CPU.

关键词： Artificial Intelligence MCTS FPGA

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