The proceedings contain 34 papers. The topics discussed include: exploring approximate computing and near-threshold operation to design energy-efficient multipliers;accuracy and size trade-off of a cartesian genetic p...
ISBN:
(纸本)9781665421706
The proceedings contain 34 papers. The topics discussed include: exploring approximate computing and near-threshold operation to design energy-efficient multipliers;accuracy and size trade-off of a cartesian genetic programming flow for logic optimization;injection-locked ring oscillator based phase-locked-loop for 1.6 Gbps clock recovery;high-performance design for the AV1 multi-alphabet arithmetic decoder;exploring constant signal propagation to optimize neural network circuits;a latching current limiter with telemetries for space applications;and configurable approximate hardware accelerator to compute SATD and SAD metrics for low power all-intra high efficiency video coding.
The proceedings contain 36 papers. The topics discussed include: a temperature-aware analysis of latched comparators for smart vehicle applications;a radio-frequency real-time spectrum sensor based on an analog signal...
ISBN:
(纸本)9781450351065
The proceedings contain 36 papers. The topics discussed include: a temperature-aware analysis of latched comparators for smart vehicle applications;a radio-frequency real-time spectrum sensor based on an analog signal processing magnitude calculator;low power IEEE 802.11ah receiver system-level design aiming for IoT applications;modeling of a MOS ultralow voltage oscillator: experimental results;low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing;and low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard.
The proceedings contain 41 papers. The topics discussed include: sizing CMOS circuits by means of the gm/ID methodology and a compact model;synergistic modeling and optimization for nanometer IC design/manufacturing i...
ISBN:
(纸本)9781605582313
The proceedings contain 41 papers. The topics discussed include: sizing CMOS circuits by means of the gm/ID methodology and a compact model;synergistic modeling and optimization for nanometer IC design/manufacturing integration;test methods for sigma-delta data converters and related devices;system-level design technologies for heterogeneous distributed systems;lithography friendly routing: from construct-by-correction to correct-by-construction;time-domain signal processing techniques;system design for 3D silicon integration;challenges of the nanoscale era;metal filling impact on standard cells: definition of the metal fill corner concept;a comparative analysis of fault injection methods via enhanced on-chip debug infrastructures;an efficient test and characterization approach for nanowire-based architectures;and implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.
The proceedings contain 45 papers. The topics discussed include: a differential low power wake-up circuit based on systematic offset for RFID applications;exploring asynchronous end-to-end communication through a sync...
ISBN:
(纸本)9781538674314
The proceedings contain 45 papers. The topics discussed include: a differential low power wake-up circuit based on systematic offset for RFID applications;exploring asynchronous end-to-end communication through a synchronous NoC;an adaptive closed-loop verification approach in UVM-SystemC for AMS circuits;a programmable gain amplifier for load demodulation channel in an NFC reader chip;hardware-oriented wedgelet evaluation skip for DMM-1 in 3D-HEVC;heavy ion microbeam experimental study of ASET on a full-custom CMOS OpAmp;a charge-sharing bandpass filter topology with boosted Q-factor in 40-nm CMOS;and a novel limiter with application in crest factor reduction techniques for wireless communications.
The proceedings contain 42 papers. The topics discussed include: design for stability of active inductor with feedback resistance;impact of ESD protection and power supply decoupling on 10 ghz low noise amplifier;desi...
ISBN:
(纸本)9781479968732
The proceedings contain 42 papers. The topics discussed include: design for stability of active inductor with feedback resistance;impact of ESD protection and power supply decoupling on 10 ghz low noise amplifier;designing ultra-low power systems with non-uniform sampling and event-driven logic;high linearity and large output swing sub-Hz pre-amplifier for portable biomedical applications;improved charge pump circuits for standard CMOS technologies;system-level design of a reconfigurable CT SD modulator for multi-standard wireless applications;crosslayer error verification, evaluation and reporting;determining cases of scenarios to improve coverage in simulation-based verification;mogamap and dynpack: and multi-objective mapping and packing algorithms for optimization of area, performance and power consumption in FPGAs.
The proceedings contain 39 papers. The topics discussed include: design of low-power 5.8-GHz ULV LNTAs using normalized biasing metric;design of low-power 5.8-GHz ULV LNTAs using normalized biasing metric;voltage coef...
ISBN:
(纸本)9798350391695
The proceedings contain 39 papers. The topics discussed include: design of low-power 5.8-GHz ULV LNTAs using normalized biasing metric;design of low-power 5.8-GHz ULV LNTAs using normalized biasing metric;voltage coefficient of resistance effect in the harmonic distortion of active-RC continuous-time sigma-delta modulators;EAVREF: an evolutionary algorithm based tool for low-power CMOS voltage reference designs;a nanomagnetic logic based processor;NoX: a compact open-source RISC-V processor for multi-processor systems-on-chip;investigating the influence of process variability on asymmetric multicore processors;an evolutionary search for energy recovery opportunities in partially reversible FCN circuits;robustness analysis of atomic silicon quantum dot logic gates;and enhancing manycore lifetime through reinforcement learning task mapping and migration.
The proceedings contain 62 papers. The topics discussed include: some experiments in test pattern generation for GPGA-implemented combinational circuits;solving the I/O bandwidth problem in system on a chip testing;te...
ISBN:
(纸本)076950843X
The proceedings contain 62 papers. The topics discussed include: some experiments in test pattern generation for GPGA-implemented combinational circuits;solving the I/O bandwidth problem in system on a chip testing;testability properties of vertex precedent BDDs;synthesis of high performance extended burst mode asynchronous state machines;analysis and design of a family of low-power class AB operational amplifiers;a generator of trapezoidal association of transistors (TAT): improving analog circuits in a pre-diffused transistor array;address satisfaction for storage files with FIFOs or stacks during scheduling of DSP algorithms;a data path synthesis method to self-testable application specific integrated circuit (ASIC);from a hyperdocument-centric to an object-oriented approach for the cave project;digital circuit design based on the resonant-tunneling-hetero-junction-bipolar-transist;on the choice of models of computation for writing executable specifications of system level designs;and prototyping a pager-like device using FPGAs: design of an object finder.
The proceedings contain 37 papers. The topics discussed include: computing at the ultimate low-energy limits;performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and hig...
ISBN:
(纸本)9781450302883
The proceedings contain 37 papers. The topics discussed include: computing at the ultimate low-energy limits;performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design;reducing and smoothing power consumption of ROM-based controller implementations;wideband ring VCO for cognitive radio five-port receiver;a high speed, highly linear CMOS fully differential track and hold circuit;systematic analysis & optimization of analog/mixed-signal circuits balancing accuracy and design time;design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference;design for reality: knowledge discovery in design and test data;low-power test in compression-based reconfigurable scan architectures;generating power-hungry test programs for power-aware validation of pipelined processors;and adaptive multi-threading for dynamic workloads in embedded multiprocessors.
The proceedings contain 35 papers. The topics discussed include: hybrid-on-chip communication architecture for dynamic MP-SoC protection;FPGA design for real time flaw detection on edges using the LEDges technique;app...
ISBN:
(纸本)9781467326087
The proceedings contain 35 papers. The topics discussed include: hybrid-on-chip communication architecture for dynamic MP-SoC protection;FPGA design for real time flaw detection on edges using the LEDges technique;application-specific network-on-chip synthesis with topology-aware floorplanning;robust modular bulk built-in current sensors for detection of transient faults;memory and communication driven spatio-temporal scheduling on MPSoCs;design-oriented delay model for CMOS inverter;extended use of pseudo-flash reset technique for an active pixel with logarithmic compressed response;yield optimization for low power current controlled current conveyor;FPGA-based digital direct-conversion transceiver for nuclear magnetic resonance systems;power consumption reduction in MPSoCs through DFS;and FPGA design methodology for DSP industrial applications - a case study of a three-phase positive-sequence detector.
The proceedings contain 38 papers. The topics discussed include: FPGA placement: dynamic decision making via machine learning;study of an avalanche compensation mirror for SiGe high performance power amplifiers dedica...
ISBN:
(纸本)9798350318340
The proceedings contain 38 papers. The topics discussed include: FPGA placement: dynamic decision making via machine learning;study of an avalanche compensation mirror for SiGe high performance power amplifiers dedicated to 5G applications;low-energy and reduced-area hardware architecture for the versatile video coding FME;secure network interface for protecting IO communication in many-cores;validating an automated asynchronous synthesis environment with a challenging design: RISC-V;power and performance costs of radiation-hardened ml inference models running on edge devices;an energy-efficient interpolation unit targeting VVC encoders with approximate adder;a wireless weatherproof acoustic sensor system to detect anomalies in substation power transformers;and jitter noise impact on analog spiking neural networks: STDP limitations.
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