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LIGHT: Lightweight Authentication for Intra embedded Integrated Electronic systems

IEEE transactions ON DEPENDABLE AND SECURE computing 2023年第2期20卷 1088-1103页

作者： Li, Xuru He, Daojing Gao, Yun Liu, Ximeng Chan, Sammy Pan, Manghan Choo, Kim-Kwang Raymond East China Normal Univ Software Engn Inst Shanghai 200062 Peoples R China Fuzhou Univ Coll Comp & Data Sci Fuzhou 350116 Peoples R China City Univ Hong Kong Dept Elect Engn Hong Kong Peoples R China Univ Texas San Antonio Dept Informat Syst & Cyber Secur San Antonio TX 78249 USA

As embedded integrated electronic systems (EIESs) become more pervasive (including in mission-critical applications), the need to ensure the security of data exchange in such a system against various malicious activities becomes more pronounced. However, designing secure and efficient solutions, such as authentication protocols, for the many different embedded systems with varying internal communication modes remains challenging. Therefore, in this paper, we propose a lightweight authenticated key-exchange (AKE) protocol for EIESs based on half-duplex and "command/response" bus. Specifically, the proposed protocol is designed to operate on resource-constrained devices, as well as having minimal number of interactions. We then prove the security of the proposed protocol and present the security parameter selection strategy for protocol implementation based on the empirical evaluations. Moreover, efficiency analysis also shows that the protocol can be effectively deployed in the EIESs environment.

关键词： Protocols Authentication Security Hash functions embedded systems Half-duplex system Costs Lightweight authentication intra embedded systems universal hash function key exchange

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Dynamic Cluster Head Selection in WSN

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ACM transactions on embedded computing systems 2024年第4期23卷 1-27页

作者： Hada, Rupendra Pratap Singh Srivastava, Abhishek Indian Inst Technol Indore Comp Sci & Engn Indore Madhya Pradesh India

A Wireless Sensor Network (WSN) comprises an ad-hoc network of nodes laden with sensors that are used to monitor a region mostly in the outdoors and often not easily accessible. Despite exceptions, several deployments of WSN continue to grapple with the limitation of finite energy derived through batteries. Thus, it is imperative that the energy of a WSN be conserved and its life prolonged. An important direction of work to this end is towards the transmission of data between nodes in a manner that minimum energy is expended. One approach to doing this is cluster-based routing, wherein nodes in a WSN are organised into clusters, and transmission of data from the node is through a representative node called a cluster-head. Forming optimal clusters and choosing an optimal cluster-head is an NP-Hard problem. Significant work is done towards devising mechanisms to form clusters and choosing cluster heads to reduce the transmission overhead to a minimum. In this article, an approach is proposed to create clusters and identify cluster heads that are near optimal. The approach involves two-stage clustering, with the clustering algorithm for each stage chosen through an exhaustive search. Furthermore, unlike existing approaches that choose a cluster-head on the basis of the residual energy of nodes, the proposed approach utilises three factors in addition to the residual energy, namely the distance of a node from the cluster centroid, the distance of a node from the final destination (base-station), and the connectivity of the node. The approach is shown to be effective and economical through extensive validation via simulations and through a real-world prototypical implementation.

关键词： embedded devices cluster head selection clustering

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Controlled Acceleration of PCM Cells Time Drift Through On-Chip Current-Induced Annealing for AIMC Multilevel MVM Computation

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IEEE transactions ON ELECTRON DEVICES 2025年第1期72卷 215-221页

作者： Antolini, Alessio Zavalloni, Francesco Lico, Andrea Vignali, Riccardo Iannelli, Luca Zurla, Riccardo Bertolini, Jacopo Calvetti, Emanuela Pasotti, Marco Scarselli, Eleonora Franchi Cabrini, Alessandro Univ Bologna Res Ctr Elect Syst Informat & Commun Technol Ercol I-40126 Bologna Italy Univ Bologna Dept Elect Elect & Informat Engn Guglielmo Marconi I-40126 Bologna Italy Univ Pavia Dipartimento Ingn Ind & Informaz I-27100 Pavia Italy STMicroelect I-27100 Pavia Italy STMicroelect Agrate Brianza Italy

This article introduces a method to mitigate conductance time drift of phase-change memory (PCM) cells for improved resilience of matrix-vector multiplication (MVM) in analog in-memory computing (AIMC) systems. The proposed approach consists of on-chip current-induced annealing of each PCM device to stabilize its conductance at a target level, avoiding any rearrangement of the cell lattice. The procedure is performed within the programming phase of PCM devices with no severe constraints on execution time because of the infrequent update of MVM weights in deep neural networks (DNNs). Experimental validations were conducted on a 90-nm STMicroelectronics CMOS Ge-rich GeSbTe (GST)-embedded PCM targeting 16 conductance levels, and results indicate that the average time drift and variability of cells conductance are reduced by at least a factor of 2.3 and 3.5, respectively, compared with standard programming. Simulations based on empirical results reveal a 0.8% MVM accuracy loss after 12 h at room temperature and 4.8% after an additional 64-h bake at 85 $<^>{\circ}$ C, with a considerable increase in MVM computing retention compared with those granted with standard programming. Accuracy loss is minimized to around 1% even at high temperatures when the proposed method is combined with hardware drift compensation.

关键词： Phase change materials Programming Annealing Lattices Standards Artificial neural networks Accuracy Phase change memory IP networks Temperature measurement Analog in-memory computing (AIMC) deep neural network (DNN) drift compensation matrix-vector multiplication (MVM) phase-change memory (PCM)

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INTOS: Persistent embedded Operating System and Language Support for Multi-threaded Intermittent computing 18

INTOS: Persistent Embedded Operating System and Language Sup...

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18th USENIX Symposium on Operating systems Design and Implementation (OSDI)

作者： Wu, Yilun Min, Byounguk Ismail, Mohannad Xiong, Wenjie Jung, Changhee Lee, Dongyoon SUNY Stony Brook Stony Brook NY 11794 USA Purdue Univ W Lafayette IN 47907 USA Virginia Tech Blacksburg VA USA

ISBN: (纸本)9781939133403

This paper introduces INTOS, an embedded operating system and language support for multi-threaded intermittent computing on a battery-less energy-harvesting platform. INTOS simplifies programming with a traditional "thread" and a "transaction" with automatic undo-logging of persistent objects in non-volatile memory. While INTOS allows the use of volatile memory for performance and energy efficiency, conventional transactions do not ensure crash consistency of volatile register and memory states. To address this challenge, INTOS proposes a novel replay-and-bypass approach, eliminating the need for users to checkpoint volatile states. Upon power restoration, INTOS recovers non-volatile states by undoing the updates of power-interrupted transactions. To reconstruct volatile states, INTOS restarts each thread bypassing committed transactions and system calls by returning recorded results without re-execution. INTOS seeks to build a persistent, full-fledged embedded OS, supporting priority-based preemptive multithreading while ensuring crash consistency even if power failure occurs during a system call or while some threads are blocked. Experiments on a commodity platform MSP430FR5994 show that when subjected to an extreme power failure frequency of 1 ms, INTOS demonstrated 1.24x lower latency and 1.29x less energy consumption than prior work leveraging idempotent processing. This trend turns out to be more pronounced on Apollo 4 Blue Plus.

关键词： Multitasking

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Distributed Task Offloading and Resource Purchasing in NOMA-Enabled Mobile Edge computing: Hierarchical Game Theoretical Approaches

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ACM transactions on embedded computing systems 2024年第1期23卷 1-28页

作者： Chen, Ying Zhao, Jie Hu, Jintao Wan, Shaohua Huang, Jiwei Beijing Informat Sci & Technol Univ Beijing 100101 Peoples R China Univ Elect Sci & Technol China Shenzhen 518110 Peoples R China China Univ Petr Beijing Peoples R China

As the computing resources and the battery capacity of mobile devices are usually limited, it is a feasible solution to offload the computation-intensive tasks generated by mobile devices to edge servers (ESs) in mobile edge computing (MEC). In this article, we study the multi-user multi-server task offloading problem in MEC systems, where all users compete for the limited communication resources and computing resources. We formulate the offloading problem with the goal of minimizing the cost of the users and maximizing the profits of the ESs. We propose a hierarchical EETORP (Economic and Efficient Task Offloading and Resource Purchasing) framework that includes a two-stage joint optimization process. Then we prove that the problem is NP-complete. For the first stage, we formulate the offloading problem as a multi-channel access game (MCA-Game) and prove theoretically the existence of at least one Nash equilibrium strategy in MCA-Game. Next, we propose a game-based multi-channel access (GMCA) algorithm to obtain the Nash equilibrium strategy and analyze the performance guarantee of the obtained offloading strategy in the worst case. For the second stage, we model the computing resource allocation between the users and ESs by Stackelberg game theory, and reformulate the problem as a resource pricing and purchasing game (PAP-Game). We prove theoretically the property of incentive compatibility and the existence of Stackelberg equilibrium. A game-based pricing and purchasing (GPAP) algorithm is proposed. Finally, a series of both parameter analysis and comparison experiments are carried out, which validate the convergence and effectiveness of the GMCA algorithm and GPAP algorithm.

关键词： Task offloading MEC game theory resource purchasing resource pricing

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Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits

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IEEE transactions ON COMPUTERS 2023年第9期72卷 2717-2725页

作者： Armeniakos, Giorgos Zervakis, Georgios Soudris, Dimitrios Tahoori, Mehdi B. Henkel, Jorg Natl Tech Univ Athens Sch Elect & Comp Engn Athens 15780 Greece Karlsruhe Inst Technol KIT Chair Embedded Syst CES Dept Comp Sci D-76131 Karlsruhe Germany Karlsruhe Inst Technol KIT D-76131 Karlsruhe Germany Univ Patras Comp Engn & Informat Dept Patras 26504 Greece KIT Chair Dependable Nano Comp CDNC Dept Comp Sci D-76131 Karlsruhe Germany KIT Chair Embedded Syst CES Dept Comp Sci D-76131 Karlsruhe Germany

Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that feature ultra-low cost, conformity, and non-toxicity requirements that silicon-based systems cannot deliver. Nevertheless, large feature sizes in PE prohibit the realization of complex printed ML circuits. In this work, we present, for the first time, an automated printed-aware software/hardware co-design framework that exploits approximate computing principles to enable ultra-resource constrained printed multilayer perceptrons (MLPs). Our evaluation demonstrates that, compared to the state-of-the-art baseline, our circuits feature on average 6x (5.7x) lower area (power) and less than 1% accuracy loss.

关键词： Approximate computing co-design multilayer perceptron printed electronics

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Introduction to the Special Issue on Memory and Storage systems for embedded and IoT Applications

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ACM transactions on embedded computing systems 2022年第1期21卷 1–2页

作者： Chang, Yuan-Hao Boukhobza, Jalil Han, Song Acad Sinica Taipei Taiwan ENSTA Bretagne Lab STICC UMR CNRS 6285 Brest France Univ Connecticut Storrs CT USA

No abstract available.

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ACE: Automated Optimization Towards Iterative Classification in Edge Health Monitors

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IEEE transactions ON BIOMEDICAL CIRCUITS AND systems 2025年第1期19卷 82-92页

作者： Wang, Yuxuan Orlandic, Lara Machetti, Simone Ansaloni, Giovanni Atienza, David Ecole Polytech Fed Lausanne EPFL Embedded Syst Lab CH-1015 Lausanne Switzerland

Wearable devices for health monitoring are essential for tracking individuals' health status and facilitating early detection of diseases. However, processing biomedical signals online for real-time monitoring is challenging due to limited computational resources on edge devices. To address this challenge, we propose an application-agnostic methodology called ACE (Automated optimization towards classification on the Edge). ACE converts a health monitoring algorithm with feature extraction and classification into an iterative detection process, incorporating algorithms of varying complexities and minimizing re-computation of shared data. First, ACE decomposes a monolithic model, employing a single feature set and classifier, into multiple algorithms with different computational complexities. Then, our automatic analysis tool integrates buffering logic into these algorithms to prevent re-computation of shared computational-intensive data. The optimized algorithm is then converted into a low-level language in C for deployment. During runtime, the system initiates monitoring with the lowest complexity algorithm and iteratively involves algorithms with higher complexity without recomputing the existing data. The iteration process continues until a pre-defined confidence threshold is met. We demonstrate the effectiveness of ACE on two biomedical applications: seizure detection and emotional state classification. ACE achieves at least 28.9% and 18.9% runtime savings without any accuracy loss on a Cortex-A9 edge platform for the two benchmarks, respectively. We discuss and demonstrate how ACE can be used by designers of such biomedical algorithms to automatically optimize and deploy their applications on the edge.

关键词： Feature extraction Classification algorithms Runtime Monitoring Image edge detection Costs Circuits and systems Health monitoring edge computing runtime optimization embedded deployment iterative classification

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Three-Stage Global Channel Pruning for Resources-Limited Platform

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IEEE transactions ON NEURAL NETWORKS AND LEARNING systems 2024年第11期35卷 16153-16166页

作者： Chen, Yijie Li, Rui Li, Wanli Wang, Jilong Li, Renfa Hunan Univ Key Lab Embedded & Network Comp Hunan Prov Coll Comp Sci & Elect Engn Changsha 410082 Hunan Peoples R China Hunan Univ Hunan Engn Res Ctr Adv Embedded Comp & Intelligen Coll Comp Sci & Elect Engn Changsha 410082 Hunan Peoples R China Peng Cheng Lab Shenzhen 518066 Nanshan Peoples R China

Deep neural networks (DNNs) have demonstrated remarkable performance in many fields, and deploying them on resource-limited devices has drawn more and more attention in industry and academia. Typically, there are great challenges for intelligent networked vehicles and drones to deploy object detection tasks due to the limited memory and computing power of embedded devices. To meet these challenges, hardware-friendly model compression approaches are required to reduce model parameters and computation. Three-stage global channel pruning, which involves sparsity training, channel pruning, and fine-tuning, is very popular in the field of model compression for its hardware-friendly structural pruning and ease of implementation. However, existing methods suffer from problems such as uneven sparsity, damage to the network structure, and reduced pruning ratio due to channel protection. To solve these issues, the present article makes the following significant contributions. First, we present an element-level heatmap-guided sparsity training method to achieve even sparsity, resulting in higher pruning ratio and improved performance. Second, we propose a global channel pruning method that fuses both global and local channel importance metrics to identify unimportant channels for pruning. Third, we present a channel replacement policy (CRP) to protect layers, ensuring that the pruning ratio can be guaranteed even under high pruning rate conditions. Evaluations show that our proposed method significantly outperforms the state-of-the-art (SOTA) methods in terms of pruning efficiency, making it more suitable for deployment on resource-limited devices.

关键词： Training Heating systems Measurement Computational modeling Quantization (signal) Object detection Neurons Channel pruning layer protection sparsity training

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FPGA Implementation of Associative Processors

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IEEE transactions ON CIRCUITS AND systems II-EXPRESS BRIEFS 2023年第5期70卷 1774-1778页

作者： Tian, Hongzheng Fouda, Mohammed E. Seo, Minjun Kurdahi, F. J. Univ Calif Irvine Ctr Embedded & Cyber Phys Syst Irvine CA 92697 USA Rain Neuromorph Inc San Francisco CA 94103 USA

In order to deal with increasingly complex computing problems, an In-memory-based computation system was proposed to replace the traditional Von-Neumann architectures. In-memory computing can save the time and energy of data movement between the memory and processor to avoid the memory-wall bottleneck of traditional Von-Neumann architecture. The associative processor (AP) is such an architecture that is proposed to implement in-memory computing. Content addressable memory (CAM), as a critical part of in-memory computing, plays an important role in an AP. In this brief, we proposed a novel FPGA implementation of the AP, including the CAM and its peripheral circuits, such as the controller, data cache, instruction cache, and program counter. The design details of the whole AP architecture are described by Verilog HDL. To the best of our knowledge, this is the first work that implements an associative processor on a real-world FPGA platform.

关键词： Computer architecture Program processors Field programmable gate arrays Microprocessors Registers Decoding Integrated circuits In-memory computing associative processors FPGA

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