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BSL: Sustainable Collaborative Inference in Intelligent Transportation systems

IEEE transactions ON INTELLIGENT TRANSPORTATION systems 2023年第12期24卷 15995-16005页

作者： Luo, Chengwen Chen, Jiongzhang Feng, Xingyu Zhang, Jin Li, Jianqiang Shenzhen Univ Natl Engn Lab Big Data Syst Comp Technol Shenzhen 518060 Peoples R China

As the recent rise of intelligent transportation systems (ITS), the sensing capability of vehicles has become crucial in realizing sophisticated intelligent transportation services. Collaborative sensing, an important approach to extend the sensing coverage of individual vehicles, has become an essential component of connected vehicle systems. However, due to challenges such as privacy concerns, frequent communication interruptions, customized models, and limited available data, the application of collaborative sensing in current ITS systems is still limited. In this paper, we propose BSL, a novel multi-exit split learning-based collaborative inference system. The key innovation of BSL is the introduction of multi-exit to the split network, enabling network training and collaborative inference between distributed device nodes and the cloud in a split manner. Specifically, BSL allows the device node to dynamically collaborate with the cloud by introducing the edge mode and collaboration mode, ensuring that intelligent services provided to the device will be sustained even if the communication is interrupted, which is crucial in ITS systems. We have implemented the system and evaluated it with public dataset on different embedded devices. The results demonstrate the promising performance of BSL.

关键词： Collaborative inference sustainable computing intelligent transportation systems edge intelligence

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iNVMFS: An Efficient File System for NVRAM-Based Intermittent computing Devices

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2022年第11期41卷 3638-3649页

作者： Wu, Ying-Jan Kuo, Ching-Yu Chang, Li-Pin Natl Yang Ming Chiao Tung Univ Coll Comp Sci Dept Comp Sci Hsinchu 300 Taiwan

Developing toward battery-less, energy-harvesting designs is a promising direction for sensor-scale devices. The recent introduction of byte-addressable, nonvolatile memory (NVRAM) enables intermittent computing, which preserves as much program progress across power interruptions as possible using fine-grained checkpoints. Sensing applications strongly demand local storage for near-data processing, and there is no exception for intermittent computing devices. While checkpointing on program progress is being studied recently, there is little work regarding how sensor file systems support intermittent computing. On power recovery, although the program progress is reverted to the latest checkpoint, the storage state stays at the instant of power loss. To remedy this problem, we present a lightweight file system for efficient operations on files and checkpoints. Our design exploits the byte addressability of NVRAM and uses as much in-place byte writing as possible while guaranteeing the safety of checkpoint operations. We evaluated our design against two prior checkpoint-enabled file systems, and results show that on average, our design reduced the total time overhead and energy consumption by 77% and 78%, respectively.

关键词： File systems Random access memory Nonvolatile memory Checkpointing Ferroelectric films Sensors Writing File systems intermittent computation nonvolatile memory (NVRAM)

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Joint DNN Partition and Resource Allocation Optimization for Energy-Constrained Hierarchical Edge-Cloud systems

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IEEE transactions ON VEHICULAR TECHNOLOGY 2023年第3期72卷 3930-3944页

作者： Su, Yi Fan, Wenhao Gao, Li Qiao, Lei Liu, Yuan'an Wu, Fan Beijing Univ Posts & Telecommun Sch Elect Engn Beijing 100876 Peoples R China Beijing Univ Posts & Telecommun Beijing Key Lab Work Safety Intelligent Monitoring Beijing 100876 Peoples R China

Hierarchical edge-cloud systems collaboratively utilize the resources of both the edge server and central cloud, enabling deep neural network (DNN) partition between the edge and cloud to accelerate the inference. However, the limited energy budgets of both the edge server and central cloud restrict them from providing optimal DNN inference services. Moreover, considering the high dynamics in stochastic environments, the long-term system performance should be optimized under long-term energy constraints. How to improve the long-term DNN inference performance in such energy-constrained hierarchical edge-cloud systems is less studied by existing related works. In this paper, we aim to jointly optimize DNN partition and computing resource allocation to minimize the long-term average end-to-end delay of multiple types of deep learning (DL) tasks while guaranteeing the energy consumption of the edge server and central cloud within their energy budgets. Based on the Lyapunov optimization technique and reinforcement learning, we design a novel deep deterministic policy gradient based DNN partition and resource allocation (DDPRA) algorithm to train policy to decide DNN partition dynamically by observing the environment. Moreover, the DDPRA algorithm is embedded with a heuristic computing resource allocation (HCRA) algorithm, which effectively reduces the complexity of policy training by decoupling and optimizing the computing resource allocation separately. We analyze the complexity of our algorithms and conduct extensive simulations. The numerical results demonstrate the superiority of our algorithm in comparison with 5 other schemes in multiple scenarios.

关键词： Servers Task analysis Resource management Partitioning algorithms Cloud computing Computational modeling Delays Hierarchical edge-cloud systems DNN partition computing resource allocation end-to-end delay energy budget

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Data-Agnostic Model Poisoning Against Federated Learning: A Graph Autoencoder Approach

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IEEE transactions ON INFORMATION FORENSICS AND SECURITY 2024年 19卷 3465-3480页

作者： Li, Kai Zheng, Jingjing Yuan, Xin Ni, Wei Akan, Ozgur B. Poor, H. Vincent Univ Cambridge Dept Engn Cambridge CB3 0FA England Real Time & Embedded Comp Syst Res Ctr CISTER P-4249015 Porto Portugal Carnegie Mellon Univ CyLab Secur & Privacy Inst Pittsburgh PA 15213 USA Real Time & Embedded Comp Syst Res Ctr CISTER P-4249015 Porto Portugal Commonwealth Sci & Ind Res Org CSIRO Digital Prod & Serv Flagship Sydney NSW 2122 Australia Univ Cambridge Dept Engn Div Elect Engn Cambridge CB3 0FA England Koc Univ Ctr neXt generat Commun CXC TR-34450 Istanbul Turkiye Princeton Univ Dept Elect & Comp Engn Princeton NJ 08544 USA

This paper proposes a novel, data-agnostic, model poisoning attack on Federated Learning (FL), by designing a new adversarial graph autoencoder (GAE)-based framework. The attack requires no knowledge of FL training data and achieves both effectiveness and undetectability. By listening to the benign local models and the global model, the attacker extracts the graph structural correlations among the benign local models and the training data features substantiating the models. The attacker then adversarially regenerates the graph structural correlations while maximizing the FL training loss, and subsequently generates malicious local models using the adversarial graph structure and the training data features of the benign ones. A new algorithm is designed to iteratively train the malicious local models using GAE and sub-gradient descent. The convergence of FL under attack is rigorously proved, with a considerably large optimality gap. Experiments show that the FL accuracy drops gradually under the proposed attack and existing defense mechanisms fail to detect it. The attack can give rise to an infection across all benign devices, making it a serious threat to FL.

关键词： Federated learning model poisoning attack graph autoencoder feature correlation

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Design Guidelines for 2.5-D Packages Featuring Organic Interposer With Bridges embedded

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IEEE transactions ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 2024年第11期14卷 1936-1942页

作者： Lai, Yangyang Takahashi, Atsushi Park, Seungbae SUNY Binghamton Dept Mech Engn Binghamton NY 13904 USA Nagase & Co Ltd Tokyo 1008142 Japan

The rapid advancement of artificial intelligence (AI) has propelled the demand for high-performance computing (HPC) systems capable of handling vast amounts of data. This necessitates improvements in data processing speed within system-on-chip (SoC) units and efficient data transmission between SoC and high-bandwidth memory (HBM). Advanced packaging solutions, particularly the silicon interposer and organic interposer, have emerged to address these challenges. This article delves into the thermo-mechanical performance of 2.5-D packages with an organic interposer, focusing on warpage management during fabrication and stress analysis induced by coefficient of thermal expansion (CTE) mismatches. The study employs finite element analysis (FEA) modeling to evaluate the impact of various factors on warpage behavior and stress levels. Parametric studies on material selection and interposer geometric design reveal crucial insights. Specifically, reducing bridge die and redistribution layer (RDL) thickness mitigates warpage at the controlled collapse chip connection (C4) level, albeit with adverse effects on BGA level warpage. Material selection significantly influences warpage behavior. Organic materials with higher CTE reduce the mismatch between the interposer and the substrate but it is adverse for the interconnection between chiplets and interposer. Moreover, stress analysis indicates the organic interposer's effectiveness in reducing interconnection stress compared to silicon interposers. This research contributes valuable insights into the design and optimization of advanced packages with bridges embedded in organic interposers, providing guidelines for material selection and geometric design to enhance reliability and functionality. The findings facilitate the development of advanced packaging solutions capable of meeting the demands of AI-driven applications in challenging operational environments.

关键词： Bridge dies organic interposer silicon inter- poser silicon inter- poser thermo-mechanical reliability warpage control warpage control warpage control

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MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge

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IEEE transactions ON CIRCUITS AND systems I-REGULAR PAPERS 2024年第5期71卷 2105-2118页

作者： Guella, Flavia Valpreda, Emanuele Caon, Michele Masera, Guido Martina, Maurizio Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy

The optimization of neural networks (NNs) is necessary to enable their deployment on energy-constrained devices. State-of-the-art methods leverage approximate multipliers to execute NNs reducing the inference energy without heavily affecting the accuracy. However, previous works usually require a specialized hardware accelerator and are limited to fixed multipliers or reconfigurable ones with few approximation levels. This paper introduces MARLIN, a framework to deploy layerwise approximate NNs on PULP, a microcontroller with a RISC-V core. A multiplier architecture, with runtime selection of 256 approximation levels, is developed and integrated into the PULP cluster cores, enabling runtime configuration through control status register (CSR) instructions embedded within the code. The PULP toolchain is adapted to incorporate the approximation level selection within the instruction flow seamlessly. MARLIN leverages the genetic algorithm NSGA-II to search for the best configurations among thousands of approximate NNs. The framework is validated by simulating an approximate NN trained with the MNIST dataset on PULP. Moreover, MARLIN is used to optimize and approximate six ResNet models trained with the CIFAR-10 dataset. In particular, for ResNet-56, the most complex NN used in the experiments, the multiplication energy is reduced by 23.9% while retaining 99% of the accuracy of the exact model.

关键词： Artificial neural networks Runtime Hardware acceleration Arithmetic Adaptation models Quantization (signal) Internet of Things Approximate computing neural networks RISC-V hardware acceleration reconfigurable computing

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Stash: Flexible Energy Storage for Intermittent Sensors

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ACM transactions on embedded computing systems 2024年第2期23卷 1-23页

作者： Alsubhi, Arwa Babatunde, Simeon Tobias, Nicole Sorber, Jacob Clemson Univ Sch Comp 821 McMillan Rd Clemson SC 29631 USA

Batteryless sensors promise a sustainable future for sensing, but they face significant challenges when storing and using environmental energy. Incoming energy can fluctuate unpredictably between periods of scarcity and abundance, and device performance depends on both incoming energy and how much a device can store. Existing batteryless devices have used fixed or run-time selectable front-end capacitor banks to meet the energy needs of different tasks. Neither approach adapts well to rapidly changing energy harvesting conditions, nor does it allow devices to store excess energy during times of abundance without sacrificing performance. This article presents Stash, a hardware back-end energy storage technique that allows batteryless devices to charge quickly and store excess energy when it is abundant, extending their operating time and carrying out additional tasks without compromising the main ones. Stash performs like a small capacitor device when small capacitors excel and like a large capacitor device when large capacitors excel, with no additional software complexity and negligible power overhead. We evaluate Stash using two applicationsaATtemperature sensing and wearable activity monitoringaATunder both synthetic solar energy and recorded solar and thermal traces from various human activities. Our results show that Stash increased sensor coverage by up to 15% under variable energy-harvesting conditions when compared to competitor configurations that used fixed small, large, and reconfigurable front-end energy storage.

关键词： Batteryless intermittent computing energy harvesting

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AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators

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ACM transactions on embedded computing systems 2023年第5期22卷 1-26页

作者： Sahoo, Siva Satyendra Ullah, Salim Kumar, Akash Interuniv Microelect Ctr IMEC 1 Kapeldreef 75 B-3001 Leuven Belgium Tech Univ Dresden Cfaed Dresden Germany Barkhausen Bau Flugel D Georg Schumann Str 11 D-01069 Dresden Germany

Approximate computing (AxC) provides the scope for achieving disproportionate gains in a system's power, performance, and area (PPA) metrics by leveraging an application's inherent error-resilient behavior (BEHAV). Trading computational accuracy for performance gains makes AxC an attractive proposition for implementing computationally complex AI/ML-based applications on resource-constrained embedded systems. The growing diversity of application domains using AI/ML has also led to the increasing usage of FPGA-based embedded systems. However, implementing AxC for FPGAs has primarily been limited to the post-processing of ASIC-optimized approximate operators (AxOs). This approach usually involves selecting from a set of AxOs that have been optimized for a gate-based implementation in an ASIC. While such an approach does allow leveraging existing knowledge of ASIC-based AxO design, it limits the scope for considering the challenges and opportunities associated with FPGA's LUT-based computation structures. Similarly, the few works considering the LUT-based computing for AxO design use generic optimization approaches that do not allow integrating problem-specific prior knowledge-empirical and/or statistical. To this end, we propose a novel tree search-based approach to AxO synthesis for FPGAs. Specifically, we present a design methodology using Monte Carlo Tree Search (MCTS)-based search tree traversal that allows the designer to integrate statistical data, such as correlation, into the AxOs optimization. With the proposed methods, we report improvements over standard MCTS algorithm-based results as well as improved hypervolume for both operator-level and application-specific DSE, compared to state-of-the-art design methodologies.

关键词： Approximate computing arithmetic operator design circuit synthesis AI-based exploration computer arithmetic automated hardware design Monte Carlo Tree Search

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TVTAC: Triple Voltage Threshold Approximate Cache for Energy Harvesting Nonvolatile Processors

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第12期43卷 4546-4557页

作者： Hosseininia, Mohammad Salahvarzi, Arash Monazzah, Amir Mahdi Hosseini Iran Univ Sci & Technol Dept Comp Engn Tehran *** Iran

Energy harvesting is considered to be a substitute for batteries in many modern systems. systems based on energy harvesting receive environmental energies from sources, such as sun, radio frequency, wind, vibration, etc, and convert them to electrical energy to be used by the capacitor of the system or feed the cyber-physical system (CPS) system directly. Despite its advantages, energy harvesting comes with some limitations, such as the instability of the received energy, which means that the energy may not be received for a moment due to environmental conditions during energy harvesting. Therefore, due to not receiving enough energy, the system function may face problems, which can lead to system shutdown and data loss. To prevent program execution interruption caused by frequent power interruptions in systems based on energy harvesting, these systems use nonvolatile processor (NVP). Saving the state in the NVP is done through nonvolatile registers and memories that can hold the contents until the power is restored. However, systems based on energy harvesting and NVPs also have challenges, such as frequent backups' energy consumption, slow program forward progress, and loss of data. In this article, we propose TVTAC, a framework for energy harvesting-based NVP CPS systems. TVTAC modifies conventional NVP's cache architecture to efficiently work with newly introduced operational mode to prevent unnecessary backup operations. Furthermore, TVTAC is equipped with an NVP's specific approximation unit that controls the approximation knobs during the approximate data cache accesses in order to save more energy. The simulation results show that TVTAC improves forward progress by 28% in the best case and 12% on average, compared to similar methods. From an energy consumption perspective, TVTAC reduces energy consumption by 43.5% in the best case and 28.5% on average.

关键词： embedded systems energy harvesting Approximate computing nonvolatile processors nonvolatile processors energy harvesting nonvolatile processors

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BlueVisor: Time-Predictable Hardware Hypervisor for Many-Core embedded systems

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IEEE transactions ON COMPUTERS 2022年第9期71卷 2205-2218页

作者： Jiang, Zhe Wei, Ran Dong, Pan Zhuang, Yan Audsley, Neil C. Gray, Ian ARM Ltd Cent Engn Dept Cambridge CB1 9NJ England Univ York York YO10 5DD N Yorkshire England Dalian Univ Technol Sch Artificial Intelligence Dalian 116024 Peoples R China Natl Univ Def Technol Sch Comp Changsha 410073 Peoples R China City Univ London Sch Math Comp Sci & Engn London EC1V 0HB England

Whilst virtualization was once restricted to large-scale computing platforms, it is now widely deployed on modern embedded computing systems. This has been driven by the availability of hardware support which alleviates the performance penalties incurred by traditional software virtualization technologies. In the domain of hard real-time systems, specialist virtualization technology which respects restricted timing requirements and constraints can be deployed to allow sharing of processors. However, other aspects of the embedded system (I/O, memory, and communication) are harder to analyze. In this paper, we argue that in order to support real-time virtualization on modern embedded systems, additional system-wide hardware support is required. We propose BlueVisor, an analyzable and scalable hardware hypervisor for many-core embedded systems, which enables time-predictable CPU, memory, and I/O virtualization, as well as supporting a fast interrupt handler, and inter-VM communication. We describe the design and implementation of the real-time hypervisor, and demonstrate how a BlueVisor-based virtualization system can be leveraged to meet real-time requirements with significant improvement in system performance, and with a low-performance cost when executing different types of software.

关键词： Virtualization Hardware Software Virtual machine monitors Real-time systems Program processors Device drivers Real-time systems hypervisor hardware software co-design scalability analyzability virtualization

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