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An embedded vertical‐federated feature selection algorithm based on particle swarm optimisation

CAAI transactions on Intelligence Technology 2023年第3期8卷 734-754页

作者： Yong Zhang Ying Hu Xiaozhi Gao Dunwei Gong Yinan Guo Kaizhou Gao Wanqiu Zhang School of Information and Control Engineering China University of Mining and TechnologyXuzhouChina The Key Laboratory of Symbolic Computation and Knowledge Engineering of Ministry of Education Jilin UniversityChangchunChina School of Computing University of Eastern FinlandKuopioFinland The Macao Institute of Systems Engineering Macao University of Science and TechnologyTaipaChina

In real life,a large amount of data describing the same learning task may be stored in different institutions(called participants),and these data cannot be shared among par-ticipants due to privacy *** case that different attributes/features of the same instance are stored in different institutions is called vertically distributed *** pur-pose of vertical‐federated feature selection(FS)is to reduce the feature dimension of vertical distributed data jointly without sharing local original data so that the feature subset obtained has the same or better performance as the original feature *** solve this problem,in the paper,an embedded vertical‐federated FS algorithm based on particle swarm optimisation(PSO‐EVFFS)is proposed by incorporating evolutionary FS into the SecureBoost framework for the first *** optimising both hyper‐parameters of the XGBoost model and feature subsets,PSO‐EVFFS can obtain a feature subset,which makes the XGBoost model more *** the same time,since different participants only share insensitive parameters such as model loss function,PSO‐EVFFS can effec-tively ensure the privacy of participants'***,an ensemble ranking strategy of feature importance based on the XGBoost tree model is developed to effectively remove irrelevant features on each ***,the proposed algorithm is applied to 10 test datasets and compared with three typical vertical‐federated learning frameworks and two variants of the proposed algorithm with different initialisation ***-mental results show that the proposed algorithm can significantly improve the classifi-cation performance of selected feature subsets while fully protecting the data privacy of all participants.

关键词： Evolutionary optimization feature selection privacy protection vertical‐federated learning

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Optimus: An Operator Fusion Framework for Deep Neural Networks

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ACM transactions on embedded computing systems 2023年第1期22卷 1-26页

作者： Cai, Xuyi Wang, Ying Zhang, Lei Chinese Acad Sci Inst Comp Technol Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Chinese Acad Sci Zhejiang Lab Beijing Peoples R China Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China

The reduction of neural parameters and operations for the applications on embedded and IoT platforms in current deep neural network (DNN) architectures has received increasing attention. Relatively, the intermediate feature maps of such lightweight neural networks begin to grow and usually outsize the on-chip memory as the new bottleneck, which introduces considerable power-consuming off-chip memory accesses. To reduce the feature-induced memory accesses, operator fusion has been proposed to parallelize the execution of multiple convolutional layers and shown significant reduction of off-chip memory accesses. However, how to fuse the neural operators is still a challenging issue that heavily depends on both the neural network (NN) topology and the specific DNN accelerator configuration. In this work, we observed prior operator fusion approaches fail to guarantee memory-level optimality as they search in the constrained operator fusion design space. Considering the complexity of the NN topologies and the constrained resources of the DNN accelerators, we develop a novel operator fusion framework, Optimus. Optimus includes an accurate memory cost model dedicated to the scheduler to evaluate the potential operator-fusion schemes and a directed acyclic graph-based operator fusion algorithm for both off-line and on-line workload deployment scenarios, which altogether generates high-efficiency operator-fusion solutions for arbitrary networkmodels running on DNN accelerators. The experimental results show that Optimus reduces 17-75% off-chip memory accesses and obtains 1.86x-3.66x energy efficiency on state-of-the-art DNN workloads when compared to the baselines and brings significant power-efficiency boost to the DNN accelerators of different architectures and dataflows.

关键词： Neural network embedded processor memory layer fusion

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veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory computing

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IEEE transactions ON CIRCUITS AND systems I-REGULAR PAPERS 2024年第9期71卷 4169-4179页

作者： Jha, Chandan Kumar Qayyum, Khushboo Coskun, Kemal Caglar Singh, Simranjeet Hassan, Muhammad Leupers, Rainer Merchant, Farhad Drechsler, Rolf Univ Bremen Inst Comp Sci D-28359 Bremen Germany German Res Ctr Artificial Intelligence DFKI D-28359 Bremen Germany Indian Inst Technol Dept Elect Engn Mumbai 400076 India Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst D-52062 Aachen Germany Newcastle Univ Sch Engn Newcastle Upon Tyne NE1 7RU England

In-Memory computing (IMC) using memristors has gained significant interest in recent years as it addresses the issue of memory bottleneck in the von Neumann architectures. One of the most popular design styles that have been developed to perform memristor-based IMC is Memristor-Aided loGIC (MAGIC). MAGIC design style based NOR and NOT operations can be used to perform IMC on memristor crossbars. The state-of-the-art SIMPLER MAGIC tool is used to generate a mapping of any arbitrary Boolean function to MAGIC operations that are suitable for high-throughput applications. The correctness of the mapping is examined by tedious manual inspections and functional simulations which may not account for all the edge cases which is not desirable. In this work, we alleviate this issue to the best of our knowledge for the first time by proposing veriSIMPLER. veriSIMPLER is an automated formal verification methodology to ensure the functional correctness of the mapping obtained using the SIMPLER MAGIC tool. The veriSIMPLER methodology generates Boolean Satisfiability Formulas (SAT) of the mapping obtained using the SIMPLER MAGIC tool and the golden reference Verilog designs. These SAT formulas are verified against each other using the Z3 solver. The veriSIMPLER methodology identified a critical bug in the mapping obtained from the SIMPLER MAGIC tool when buffers are connected between input and output. We also propose a methodology to patch this bug to generate the correct mapping, which in turn extends the capability of the SIMPLER MAGIC tool to handle buffers on top of providing a formal verification methodology. We have used a variety of benchmark circuits from the widely used ISCAS'85, ISCAS'89, ITC'99, and IWLS'93 to show the efficacy of the veriSIMPLER methodology. We aim to make the formally verified mapping obtained using the veriSIMPLER methodology open-source to promote further research in this direction.

关键词： Memristors Logic Logic gates Formal verification Single instruction multiple data Computer architecture Computer bugs In-memory computing memristors formal verification memristor-aided logic equivalence checking

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Fuzzy-Granular Concept-Cognitive Learning via Three-Way Decision: Performance Evaluation on Dynamic Knowledge Discovery

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IEEE transactions ON FUZZY systems 2024年第3期32卷 1409-1423页

作者： Guo, Doudou Xu, Weihua Qian, Yuhua Ding, Weiping Southwest Univ Coll Artificial Intelligence Chongqing 400715 Peoples R China Shanxi Univ Inst Big Data Sci & Ind Taiyuan 030006 Peoples R China Nantong Univ Sch Informat Sci & Technol Nantong 226019 Peoples R China

Concept-cognitive learning (CCL) and three-way decision (3WD) models provide powerful techniques for knowledge discovery. Some early attempts in the field have successfully combined CCL and 3WD, i.e., three-way concept learning. However, only a few attempts were made to combine CCL with 3WD in a dynamic fuzzy context due to two challenges: 1) Three-way CCL incapability;2) The current incremental three-way concept learning mechanism is insufficient to model real-time updating cognitive procedure. Hence, this article first shows some new standpoints on improving fuzzy-based CCL accuracy and then proposes fuzzy-granular three-way concept-cognitive learning (F3WG-CCL) for concept modeling and dynamic knowledge learning. Specifically, we first define a new F3WG-concept to characterize the knowledge embedded in fuzzy data. Furthermore, a big concept priority principle and an update mechanism are borrowed for concept recognition and dynamic concept cognition. Finally, we show that F3WG-CCL can be implemented simultaneously via theoretical guarantee and sufficient experimental, including 1) achieving state-of-the-art dynamic knowledge learning;2) demonstrating that the three-way concept is effective in a fuzzy context;and 3) discovering that the big concept is valuable for fuzzy concept recognition. Our work will provide a powerful approach to research fuzzy-based CCL and dynamic knowledge discovery.

关键词： Knowledge discovery Uncertainty Task analysis Data models Computational modeling Cognition Real-time systems Concept-cognitive learning (CCL) fuzzy context granular computing (GrC) knowledge discovery three-way decision (3WD)

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Detecting Information Leakage Against Chinese Wall Policy Based on the Unfolding Technique of Colored Petri Nets

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IEEE transactions ON COMPUTATIONAL SOCIAL systems 2024年

作者： Tu, Hanqian Xiang, Dongming Ding, Zuohua Liu, Guanjun Zhejiang Sci Tech Univ Dept Comp Sci & Technol Hangzhou 310018 Peoples R China Tongji Univ Minist Educ Dept Comp Sci Key Lab Embedded Syst & Serv Comp Shanghai 201804 Peoples R China Tongji Univ Shanghai Elect Transact & Informat Serv Collaborat Shanghai 201804 Peoples R China

Information leakage easily occurs in large-scale information interactions and brings harm to individuals, enterprises, and society. As a well-known security policy, Chinese Wall (CW) provides a security guideline, which combines mandatory and discretionary access control to avoid information leakage. Colored Petri nets (CPNs) are a widely used formal method, well suited for verification of CW policy due to the capability of characterizing the concurrency. However, CPN easily suffers from the problem of state space explosion due to the interleaving semantics. The unfolding techniques can effectively alleviate this problem. In this article, we apply simplified CPN and their unfolding techniques to detect information leakage against CW policy. Specifically, we define a CPN-based CW model, propose an algorithm to generate the merged process of CPN, and detect the potential information leakage by analyzing the structural behaviors of its unfoldings. Furthermore, we conduct a case study and several experiments to show the advantages of our method. The results exhibit that our method can effectively detect information leakage against CW policy and alleviate the state space explosion.

关键词： Color Information leakage Petri nets Explosions Concurrent computing Information systems Analytical models Space exploration Semantics Computer science Chinese Wall (CW) policy colored Petri net (CPN) information leakage unfolding techniques

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Power-Aware Checkpointing for Multicore embedded systems

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IEEE transactions ON PARALLEL AND DISTRIBUTED systems 2022年第12期33卷 4410-4424页

作者： Ansari, Mohsen Safari, Sepideh Khdr, Heba Gohari-Nazari, Pourya Henkel, Joerg Ejlali, Alireza Hessabi, Shaahin Sharif Univ Technol Dept Comp Engn Tehran 14588 Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran *** Iran Karlsruhe Inst Technol D-76131 Karlsruhe Germany

Increasing the number of cores integrated on a single chip offers a great potential for the implementation of fault-tolerant techniques to achieve high reliability in real-time embedded systems. Checkpointing with rollback-recovery is a well-established technique to tolerate transient faults in multicore platforms. To consider the worst-case fault occurrence scenario, checkpointing technique requires to re-execute some parts of the tasks, and that might lead to simultaneous execution of task parts with high power consumptions, which eventually might result in a peak power increase beyond the thermal design power (TDP). Exceeding TDP can elevate on-chip temperatures beyond safe limits, and thereby triggering countermeasures that throttle down the voltage and frequency levels or power gate the cores. Such countermeasures might lead to violating task deadlines and degrading the system's reliability. To avoid such severe scenarios, it is inevitable to consider the impact of applying fault-tolerant techniques on the power consumption and prevent violating the power constraint of the chip, i.e., TDP. This article presents for the first time, a peak-power-aware checkpointing (PPAC) technique that tolerates a given number of faults, k, while at the same time meets the power constraint in hard real-time embedded systems. To do this, our proposed technique (PPAC) adjusts the timing of the checkpoints, which have lower power consumption than the tasks to the execution time points that have power spikes beyond TDP. Moreover, PPAC exploits the available slack times on the cores to delay the execution of some tasks to avoid the remaining power spikes beyond TDP, which could not be mitigated by solely adjusting checkpoints. To evaluate our technique, we extend the state-of-the-art system-level simulator, gem5, with the state-of-the-art checkpointing module in Linux. Our experimental results show that our proposed technique is able to tolerate a given number of faults without excee

关键词： Task analysis Checkpointing Timing Power demand Real-time systems embedded systems Reliability Peak power consumption checkpointing multicore platforms embedded systems

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CrISA-X: Unleashing Performance Excellence in Lightweight Symmetric Cryptography for Extendable and Deeply embedded Processors

IACR Transactions on Cryptographic Hardware and Embedded Sys...

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IACR transactions on Cryptographic Hardware and embedded systems 2024年第3期2024卷 377-417页

作者： Ganon, Oren Levi, Itamar Bar-Ilan University Ramat-Gan Israel

The efficient execution of a Lightweight Cryptography (LWC) algorithm is essential for edge computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. We propose the CrISA-X-a Cryptography Instruction Set Architecture eXtensions designed to improve cryptographic latency on extendable ***-X, provides enhanced speed of various algorithms simultaneously while optimizing ISA adaptability, a feat yet to be accomplished. The extension, diverse for several computation levels, is first tailored explicitly for individual algorithms and sets of LWC algorithms, depending on performance, frequency, and area trade-offs. By diligently applying the Min-Max optimization technique, we have configured these extensions to achieve a delicate balance between performance, area utilization, code size, etc. Our study presents empirical evidence of the performance enhancement achieved on a synthesis modular RISC processor. We offer a framework for creating optimized processor hardware and ISA extensions. The CrISA-X outperforms ISA extensions by delivering significant performance boosts between 3x to 17x while experiencing a relative area cost increase of +12% and +47% in LUTs. Notably, as one important example, the utilization of the ASCON algorithm yields a 10x performance boost in contrast to the base ISA instruction implementation. © 2024, Ruhr-University of Bochum. All rights reserved.

关键词： Cryptography

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SG-Float: Achieving Memory Access and computing Power Reduction Using Self-Gating Float in CNNs

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ACM transactions on embedded computing systems 2023年第6期22卷 1-22页

作者： Wu, Jun-Shen Hsu, Tsen-Wei Liu, Ren-Shuo Department of Electrical Engineering National Tsing Hua University No. 101 Section 2 Kuang-Fu Road Hsinchu300044 Taiwan

Convolutional neural networks (CNNs) are essential for advancing the field of artificial intelligence. However, since these networks are highly demanding in terms of memory and computation, implementing CNNs can be challenging. To make CNNs more accessible to energy-constrained devices, researchers are exploring new algorithmic techniques and hardware designs that can reduce memory and computation *** this work, we present self-gating float (SG-Float), algorithm hardware co-design of a novel binary number format, which can significantly reduce memory access and computing power requirements in CNNs. SG-Float is a self-gating format that uses the exponent to self-gate the mantissa to zero, exploiting the characteristic of floating-point that the exponent determines the magnitude of a floating-point value and the error tolerance property of CNNs. SG-Float represents relatively small values using only the exponent, which increases the proportion of ineffective mantissas, corresponding to reducing mantissa multiplications of floating-point numbers. To minimize the accuracy loss caused by the approximation error introduced by SG-Float, we propose a fine-tuning process to determine the exponent thresholds of SG-Float and reclaim the accuracy loss. We also develop a hardware optimization technique, called the SG-Float buffering strategy, to best match SG-Float with CNN accelerators and further reduce memory access. We apply the SG-Float buffering strategy to vector-vector multiplication processing elements (PEs), which NVDLA adopts, in TSMC 40nm technology. Our evaluation results demonstrate that SG-Float can achieve up to 35% reduction in memory access power and up to 54% reduction in computing power compared with AdaptivFloat, a state-of-the-art format, with negligible power and area overhead. Additionally, we show that SG-Float can be combined with neural network pruning methods to further reduce memory access and mantissa multiplications in pruned CNN models

关键词： computing power

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SPI Verification Monitor Module Using UVM 10

SPI Verification Monitor Module Using UVM

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10th International Conference on Advanced computing and Communication systems, ICACCS 2024

作者： Kadambarajan, Jeya Prakash Kadarkarai, Pandiaraj Kalyani, Budda Bathul, Mohammad Rabiya Sandhya, Theerdhala Greeshma, Malasani Kalasalingam Academy of Research and Education Electronics and Communication Engineering Department Virudhunagar India

ISBN: (纸本)9798350384369

The Serial Peripheral Interface (SPI) protocol remains a cornerstone in modern embedded systems, demanding rigorous and efficient verification methodologies to ensure functional correctness. This paper presents the design and implementation of an SPI verification monitor module using the Universal Verification Methodology (UVM). The monitor is tailored to observe, track, and validate SPI transactions within a testbench environment. The paper details the SPI protocol's intricacies and challenges during verification, emphasizing the need for robust monitoring solutions. Leveraging UVM's structure and methodology, the monitor module is architected to capture and analyse SPI interface behaviors, including data transfers, clocking, and control signals. Implementation details encompassing the monitor's interaction with the design under test (DUT) through a comprehensive testbench infrastructure are elucidated. The verification flow incorporates sequences, drivers, and a scoreboard within the UVM framework, ensuring thorough validation against expected behaviors. Simulation results demonstrate the efficacy of the monitor in detecting protocol violations, timing discrepancies, and data integrity issues. The findings underscore the effectiveness of the proposed SPI verification monitor in facilitating systematic verification and its potential for integration into complex digital systems. © 2024 IEEE.

关键词： Design Under Test (DUT) Monitor Module Protocol Violations SPI Protocol SPI transactions Testbench Universal Verification Methodology (UVM) Verification Flow Verification Methodologies

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Energy-Aware Heterogeneous Federated Learning via Approximate DNN Accelerators

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IEEE transactions on Computer-Aided Design of Integrated Circuits and systems 2025年第6期44卷 2054-2066页

作者： Pfeiffer, Kilian Balaskas, Konstantinos Siozios, Kostas Henkel, Jorg Karlsruhe Institute of Technology Chair for Embedded Systems Karlsruhe76131 Germany University of Patras Department of Computer Engineering and Informatics Patras26504 Greece Aristotle University of Thessaloniki Department of Physics Thessaloniki54124 Greece

In Federated Learning (FL), devices that participate in the training usually have heterogeneous resources, i.e., energy availability. In current deployments of FL, devices that do not fulfill certain hardware requirements are often dropped from the collaborative training. However, dropping devices in FL can degrade training accuracy and introduce bias or unfairness. Several works have tackled this problem on an algorithm level, e.g., by letting constrained devices train a subset of the server neural network (NN) model. However, it has been observed that these techniques are not effective w.r.t. accuracy. Importantly, they make simplistic assumptions about devices’ resources via indirect metrics, such as multiply accumulate (MAC) operations or peak memory requirements. We observe that memory access costs (that are currently not considered in simplistic metrics) have a significant impact on the energy consumption. In this work, for the first time, we consider on-device accelerator design for FL with heterogeneous devices. We utilize compressed arithmetic formats and approximate computing, targeting to satisfy limited energy budgets. Using a hardware-aware energy model, we observe that, contrary to the state of the art’s moderate energy reduction, our technique allows for lowering the energy requirements (by 4× ) while maintaining higher accuracy. © 1982-2012 IEEE.

关键词： Budget control

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