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GHOST: A Graph Neural Network Accelerator using Silicon Photonics

ACM transactions on embedded computing systems 2023年第5期22卷 1-25页

作者： Afifi, Salma Sunny, Febin Shafiee, Amin Nikdast, Mahdi Pasricha, Sudeep Colorado State Univ Dept Elect & Comp Engn 1373 campus delivery Ft Collins CO 80523 USA

Graph neural networks (GNNs) have emerged as a powerful approach for modelling and learning from graphstructured data. Multiple fields have since benefitted enormously from the capabilities of GNNs, such as recommendation systems, social network analysis, drug discovery, and robotics. However, accelerating and efficiently processing GNNs require a unique approach that goes beyond conventional artificial neural network accelerators, due to the substantial computational and memory requirements of GNNs. The slowdown of scaling in CMOS platforms also motivates a search for alternative implementation substrates. In this paper, we present GHOST, the first silicon-photonic hardware accelerator for GNNs. GHOST efficiently alleviates the costs associated with both vertex-centric and edge-centric operations. It implements separately the three main stages involved in running GNNs in the optical domain, allowing it to be used for the inference of various widely used GNN models and architectures, such as graph convolution networks and graph attention networks. Our simulation studies indicate that GHOST exhibits at least 10.2 xbetter throughput and 3.8 xbetter energy efficiency when compared to GPU, TPU, CPU and multiple state-of-the-art GNN hardware accelerators.

关键词： Graph Neural Networks silicon photonics optical computing

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Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation

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ACM transactions on embedded computing systems 2023年第4期22卷 1-24页

作者： Pradhan, Chetana Letras, Martin Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Co Design Cauerstr 11 D-91058 Erlangen Germany

This article proposes a novel approach for the generation of memory-efficient table-based function approximation circuits for edge devices in general and FPGAs in particular. Given a function f (x) to be approximated in a given interval [x(0), x(0) + a) and a maximum approximation error E-a, the goal is to determine a function table implementation with a minimized memory footprint, i.e., number of entries that need to be stored. Rather than state-of-the-art work performing an equidistant sampling of the given interval by so-called breakpoints and using linear interpolation between two adjacent breakpoints to determine f (x) at the maximum error bound, we propose and compare three algorithms for splitting the given interval into sub-intervals to reduce the required memory footprint drastically based on the observation that in sub-intervals of low gradient, a coarser sampling grid may be assumed while guaranteeing the maximum interpolation error bound E-a. Experiments on elementary mathematical functions show that a large fraction in memory footprint may be saved. Second, a hardware architecture implementing the sub-interval selection, breakpoint lookup, and interpolation at a latency of just 9 clock cycles is introduced. Third, for each generated circuit design, BRAMs are automatically instantiated rather than synthesizing the reduced footprint function table using LUT primitives, providing an additional degree of resource efficiency. The approach presented here for FPGAs can equally be applied to other circuit technologies for fast and, at the same time, memory-optimized function approximation at the edge.

关键词： FPGA approximate computing function approximation BRAM

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TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs 19th

TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM o...

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19th International Symposium on Applied Reconfigurable computing (ARC) - Architectures, Tools, and Applications

作者： Knoedtel, Johannes Hernandez, Hector Gerardo Munoz Lehnert, Alexander Thieu, Gia Bao Gesper, Sven Paya-Vaya, Guillermo Reichenbach, Marc Brandenburg Univ Technol Cottbus Senftenberg Chair Comp Engn Cottbus Germany Univ Rostock Inst Appl Microelect & Comp Engn Rostock Germany Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Braunschweig Germany

ISBN: (纸本)9783031429200;9783031429217

The use of High Bandwidth Memory (HBM) is one way to solve the bottleneck of memory bandwidth limitation. Furthermore, the integration of HBM memories in Field Programmable Gate Arrays (FPGA) now also makes it possible to use this memory technology in a wide range of applications and even in embedded systems. Nevertheless, the use of HBM poses major challenges for architecture development. In addition to highly parallel access, high latencies must be hidden. Furthermore, the partitioning of the data and the bus structure play a decisive role. Finally, memory controller implementations are mostly vendor specific making it difficult to predict the exact performance of the memory subsystem. In this paper, we present TAPRE-HBM, an FPGA-based rapid prototyping platform for analyzing computer architectures with HBM memory backends. The goal of this work is to evaluate and assess the impact of particular memory access patterns. As these patterns are an emerging property of the architecture and application, such traces can be created by simulating the target computer architectures which should use the HBM memory subsystem without the need for a specific implementation or integration. Any incurred latency will be revealed by this method, even if only a system-level model exists. Using the FPGA-based rapid prototyping platform, performance predictions can be made and thus it can be determined whether the selected target architecture or software running on the target architecture is suitable for use with HBM memories. The proposed platform is analyzed using a vector processor as an example and present various optimizations to increase the memory bandwidth. Compared to other works, a high number of memory transactions can be simulated on real hardware, with a high memory interface frequency and arbitrary delays between transactions.

关键词： embedded systems

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A Hardware-Friendly Real-Time Implementation of the Auditory Attention Based on a Novel Spiking Winner-Take-All Network

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2023年第8期42卷 2566-2579页

作者： Abdoli, Behrooz Safari, Saeed Univ Tehran Coll Engn Sch Elect & Comp Engn High Performance Embedded Architecture Lab Tehran 0098 Iran

In recent decades, the modeling and designing of neuromorphic systems have received considerable attention, leading to the development of electrophysiological devices that can mimic the dynamic behavior of cortical networks. Some features, such as parallel processing, real-time performance, reconfigurability, low production cost, and good accuracy, make field-programmable gate arrays (FPGAs) an ideal hardware platform for implementing spiking neural networks (SNNs), which has become very popular in the field of neural computing. In this work, we investigated a high-performance FPGA design of the auditory attention (AA) to simulate the on-chip "cocktail party" effect similar to what happens in the brain. In the first step, we introduce a novel spiking winner-take-all (SWTA) network consisting of a hardware-friendly Izhikevich neuron model and explore its biological characteristics and stability. We then use this network as a receptive field in the primary auditory cortex, which is tuned by attention signals. The desired sound frequency will be selected as the target and transmitted to the higher layers of the auditory cortex for further processing, while other frequencies are severely suppressed. Experimental results show that the proposed network accurately follows the dynamic behavior defined in the AA theory and emphasizes the resource consumption after post place and routes on a fully efficient hardware implementation, where less than 4% of the resources were used to implement a network with 1856 neurons.

关键词： Auditory attention (AA) field-programmable gate array (FPGA) neuromorphic hardware spiking neural network (SNN) winner-take-all (WTA)

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GRADES: Gradient Descent for Similarity Caching

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IEEE-ACM transactions ON NETWORKING 2023年第1期31卷 30-41页

作者： Sabnis, Anirudh Salem, Tareq Si Neglia, Giovanni Garetto, Michele Leonardi, Emilio Sitaraman, Ramesh K. Univ Massachusetts Coll Informat & Comp Sci Amherst MA 01003 USA Univ Cote dAzur INRIA F-06902 Sophia Antipolis France Univ Torino Dipartimento Informat I-10149 Turin Italy Politecn Torino I-10129 Turin Italy

A similarity cache can reply to a query for an object with similar objects stored locally. In some applications of similarity caches, queries and objects are naturally represented as points in a continuous space. This is for example the case of 360 degrees videos where user's head orientation-expressed in spherical coordinates-determines what part of the video needs to be retrieved, or of recommendation systems where a metric learning technique is used to embed the objects in a finite dimensional space with an opportune distance to capture content dissimilarity. Existing similarity caching policies are simple modifications of classic policies like LRU, LFU, and qLRU and ignore the continuous nature of the space where objects are embedded. In this paper, we propose Grades, a new similarity caching policy that uses gradient descent to navigate the continuous space and find appropriate objects to store in the cache. We provide theoretical convergence guarantees and show Grades increases the similarity of the objects served by the cache in both applications mentioned above.

关键词： Content distribution networks approximate computing

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An Efficient BCNN Deployment Method Using Quality-Aware Approximate computing

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2022年第11期41卷 4217-4228页

作者： Liu, Bo Wang, Ziyu Wang, Xuetao Zhang, Renyuan Xue, Anfeng Shen, Qiao Xie, Na Gong, Yu Wang, Zhen Yang, Jun Cai, Hao Southeast Univ Natl ASIC Syst Engn Ctr Sch Elect Sci & Engn Nanjing 210096 Peoples R China Nanjing Prochip Elect Technol Co Ltd Nanjing 210001 Peoples R China

As the artificial intelligence and Internet of Things (AIoT) develop rapidly, the deployment of artificial neural networks in edge computing is becoming significant with great challenge. The binarized convolutional neural network (BCNN) is one of the most widely adopted light-weight ANNs in AIoT, which can achieve the balance of system accuracy and hardware resource consumption, compared to others. To achieve high power and area efficiency in BCNN deployment, many approximate computing (AxC) techniques are integrated to make full use of the resilience of BCNN. As the research focused on the integration of AxC in circuit design, the design of AxC itself is not fully considered when applied to specific applications or domains. Based on circuit-architecture-system co-design, this article proposes an efficient BCNN deployment method, including a quality-circuit co-design method for approximate adder generation, a quality-aware intercompensation approach for addition tree, and a computing quality involved retraining approach for BCNN deployment. Experimental results show that the proposed quality model can achieve 86.43% in average accuracy while evaluating nine types of typical approximate adders. The proposed method is conducted on the applications of keyword spotting of GSCD, MNIST, and CIFAR-10, and we can further rise the approximation degree by 50%-75%, while reducing the accuracy by less than 1%.

关键词： Adders Approximate computing Hardware Approximation algorithms Circuit synthesis Analytical models Computational modeling Approximate adder approximate computing (AxC) binarized convolutional neural network (BCNN) computing quality

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computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2023年第11期42卷 3665-3678页

作者： Bai, Zhenyu Casse, Hugues Carle, Thomas Rochange, Christine Univ Toulouse IRIT CNRS Toulouse INPUT3 F-31062 Toulouse France

We propose a precise and efficient pipeline analysis to tackle the problem of out-of-order resources in modern embedded microprocessors for the computation of the worst-case execution time (WCET). Such resources are prone to timing anomalies (Reineke et al., 2006). To remain sound, the timing analysis must either rely on huge timing over-estimations or consider all possible pipeline states which usually leads to a combinatorial blowup. To cope with this situation, we build an efficient computational model by leveraging the algebraic properties of the execution decision diagram (Bai et al., 2020) which is able to track precisely all pipeline states all along the execution paths of the analyzed program while keeping the analysis time within acceptable range. We show how to apply this analysis at the control flow graph (CFG) level, and how to account for a typical out-of-order resource: the shared memory bus between the instruction and data caches. We observe a gain in precision of the WCET ranging from 20% to 80% compared to the state-of-the-art pipeline analysis of the OTAWA WCET toolset. The analysis time shows that our approach scales to realistic benchmarks, making it appropriate for industrial applications.

关键词： Pipeline real time static analysis worst-case execution time (WCET)

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AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2023年第6期42卷 2074-2078页

作者： Danopoulos, Dimitrios Zervakis, Georgios Siozios, Kostas Soudris, Dimitrios Henkel, Joerg Natl Tech Univ Athens Sch Elect & Comp Engn Athens 15780 Greece Karlsruhe Inst Technol Chair Embedded Syst D-76131 Karlsruhe Germany Aristotle Univ Thessaloniki Dept Phys Thessaloniki 54124 Greece

Current state-of-the-art employs approximate multipliers to address the highly increased power demands of deep neural network (DNN) accelerators. However, evaluating the accuracy of approximate DNNs is cumbersome due to the lack of adequate support for approximate arithmetic in DNN frameworks. We address this inefficiency by presenting AdaPT, a fast emulation framework that extends PyTorch to support approximate inference as well as approximation-aware retraining. AdaPT can be seamlessly deployed and is compatible with the most DNNs. We evaluate the framework on several DNN models and application fields, including CNNs, LSTMs, and GANs for a number of approximate multipliers with distinct bitwidth values. The results show substantial error recovery from approximate retraining and reduced inference time up to 53.9x with respect to the baseline approximate implementation.

关键词： Accelerator approximate computing deep neural network (DNN) PyTorch quantization

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Towards a New Thermal Monitoring Based Framework for embedded CPS Device Security

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IEEE transactions ON DEPENDABLE AND SECURE computing 2022年第1期19卷 524-536页

作者： Patel, Naman Krishnamurthy, Prashanth Amrouch, Hussam Henkel, Joerg Shamouilian, Michael Karri, Ramesh Khorrami, Farshad NYU Tandon Sch Engn 6 MetroTech Ctr Brooklyn NY 11201 USA Karlsruhe Inst Technol Haid & Neu Str D-776131 Karlsruhe Germany

This article introduces a thermal side channel as a proxy for the behavior of embedded processors to detect changes in the behavior in a cyber-physical system. Such changes may be due to software/hardware attacks and altered processors. Since control system processes are periodic computations, the thermal side channels exhibit a temporal pattern. This enables the detection of altered code and changed device characteristics. We present a machine learning approach to estimate the activity of the embedded device from the time sequence of thermal images and show that deviations from expected behavior can be detected. The approach is validated on a multi-core processor running a periodic computational code. The infrared imager collects thermal imagery from the processor, which is cooled from the backside. Instead of an external imager, one can deploy a finite number of on-chip temperature sensors. This article shows that integrating on-chip temperature sensors allows robust real-time monitoring of the processor behavior. Finally, we offer a machine learning approach to optimally place the on-chip sensors to aid detection.

关键词： Side-channel analysis and countermeasures embedded systems security cyber-physical systems thermal side channel real-time monitoring temperature sensors software and hardware attacks machine learning

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Probability-Driven Evaluation of Lower-Part Approximation Adders

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IEEE transactions ON CIRCUITS AND systems II-EXPRESS BRIEFS 2022年第1期69卷 204-208页

作者： Alan, Tanfer Henkel, Joerg Karlsruhe Inst Technol Chair Embedded Syst D-76131 Karlsruhe Germany

Parallel prefix adder topologies suffer from carry chains forming critical paths, limiting the performance and therefore the efficiency. We study approximation methods that offload the lower-part of calculation to an approximate unit and shorten the carry chain. We derive their accuracy models using probability theory. These models can replace Monte Carlo simulations. Furthermore, they can reveal better accuracy trade-offs without going through the RTL design, synthesis, and simulation of each unit and approximation level individually. Thus, they can eliminate the required design and simulation time and effort. After analyzing area-wise comparisons at varying number of approximated bits, we show that choosing a design that outperforms the others probabilistically also outperforms them in terms of accuracy, power, and performance trade-offs.

关键词： Adders Logic gates Computational modeling Hardware Probabilistic logic Integrated circuit modeling Circuits and systems Approximate computing arithmetic units adder low-power design energy efficiency

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