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4th International Conference on Advanced Research in computing, ICARC 2024

作者： Shamalka, M.D.M. Banujan, Kuhaneswaran Kumara, B.T.G.S. Sabaragamuwa University of Sri Lanka Department of Computing & Information Systems Sri Lanka Australia

ISBN: (纸本)9798350384864

Most of the software vendors lost their expected revenue because of the pirated software. Not only economic losses but also they face numerous kinds of problems including reputation damage. Software users are also facing a number of issues because of pirated software including legal issues because of the break of copyright protections. The aim of this research is to introduce blockchain and smart contracts-based approaches to mitigate software piracy. Software piracy remains a pervasive challenge in the digital landscape, prompting the exploration of innovative solutions to protect intellectual property rights. This research proposes a novel approach leveraging blockchain technology and smart contracts to mitigate software piracy. The proposed platform allows users to download and install software securely, with every transaction meticulously recorded on the blockchain. Through the immutability and transparency inherent in blockchain, a tamper-resistant ledger ensures the traceability of software transactions. Smart contracts, embedded in the platform, enforce licensing agreements, providing an automated and decentralized mechanism for software distribution. The integration of blockchain and smart contracts not only fortifies software protection but also introduces a transparent and auditable ecosystem. This research contributes to the discourse on combating software piracy by harnessing the power of blockchain technology, offering a robust and decentralized solution for safeguarding intellectual property in the digital era. © 2024 IEEE.

关键词： Smart contract

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A Composable Monitoring System for Heterogeneous embedded Platforms

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ACM transactions on embedded computing systems 2021年第5期20卷 1–34页

作者： Valente, Giacomo Fanni, Tiziana Sau, Carlo Di Mascio, Tania Pomante, Luigi Palumbo, Francesca Univ Aquila Laquila Italy Univ Sassari Cagliari Italy Univ Cagliari Cagliari Italy

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customiz-ability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

关键词： HW monitoring monitoring system heterogeneous system HW reconfiguration FPGA

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Robust Learning under Hybrid Noise

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ACM transactions ON INTELLIGENT systems AND TECHNOLOGY 2025年第2期16卷 1-27页

作者： Wei, Yang Chen, Shuo Ye, Shanshan Han, Bo Gong, Chen Nanjing Univ Sci & Technol Sch Comp Sci Nanjing Peoples R China RIKEN AIP Chuo ku Tokyo Japan Univ Technol Sydney Broadway Australia Hong Kong Baptist Univ Hong Kong Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing Peoples R China

Feature noise and label noise are ubiquitous in practical scenarios, which pose great challenges for training a robust machine learning model. Most previous approaches usually deal with only a single problem of either feature noise or label noise. However, in real-world applications, hybrid noise, which contains both feature noise and label noise, is very common due to the unreliable data collection and annotation processes. Although some results have been achieved by a few representation learning based attempts, this issue is still far from being addressed with promising performance and guaranteed theoretical analyses. To address the challenge, we propose a novel unified learning framework called Feature and Label Recovery (FLR) to combat the hybrid noise from the perspective of data recovery, where we concurrently reconstruct both the feature matrix and the label matrix of input data. Specifically, the clean feature matrix is discovered by the low-rank approximation, and the ground-truth label matrix is embedded based on the recovered features with a nuclear norm regularization. Meanwhile, the feature noise and label noise are characterized by their respective adaptive matrix norms to satisfy the corresponding maximum likelihood. As this framework leads to a non-convex optimization problem, we develop the non-convex Alternating Direction Method of Multipliers (ADMM) with the convergence guarantee to solve our learning objective. We also provide the theoretical analysis to show that the generalization error of FLR can be upper-bounded in the presence of hybrid noise. Experimental results on several typical benchmark datasets clearly demonstrate the superiority of our proposed method over the state-of-the-art robust learning approaches for various noises.

关键词： computing methodologies -> Machine learning Machine learning approaches Hybrid noise Matrix recovery Generalization bound

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Self Supervised Adversarial Domain Adaptation for Cross-Corpus and Cross-Language Speech Emotion Recognition

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IEEE transactions ON AFFECTIVE computing 2023年第3期14卷 1912-1926页

作者： Latif, Siddique Rana, Rajib Khalifa, Sara Jurdak, Raja Schuller, Bjorn Univ Southern Queensland USQ Springfield Qld 4301 Australia CSIRO Distributed Sensing Syst Grp Data61 Pullenvale Qld 4069 Australia Queensland Univ Technol QUT TruNets Trusted Networks Lab Brisbane Qld 4000 Australia Imperial Coll London GLAM Grp Language Audio & Mus London SW7 2BX England Univ Augsburg ZDB Chair Embedded Intelligence Hlth Care & Wellbe D-86159 Augsburg Germany

Despite the recent advancement in speech emotion recognition (SER) within a single corpus setting, the performance of these SER systems degrades significantly for cross-corpus and cross-language scenarios. The key reason is the lack of generalisation in SER systems towards unseen conditions, which causes them to perform poorly in cross-corpus and cross-language settings. Recent studies focus on utilising adversarial methods to learn domain generalised representation for improving cross-corpus and cross-language SER to address this issue. However, many of these methods only focus on cross-corpus SER without addressing the cross-language SER performance degradation due to a larger domain gap between source and target language data. This contribution proposes an adversarial dual discriminator (ADDi) network that uses the three-players adversarial game to learn generalised representations without requiring any target data labels. We also introduce a self-supervised ADDi (sADDi) network that utilises self-supervised pre-training with unlabelled data. We propose synthetic data generation as a pretext task in sADDi, enabling the network to produce emotionally discriminative and domain invariant representations and providing complementary synthetic data to augment the system. The proposed model is rigorously evaluated using five publicly available datasets in three languages and compared with multiple studies on cross-corpus and cross-language SER. Experimental results demonstrate that the proposed model achieves improved performance compared to the state-of-the-art methods.

关键词： Training Adaptation models Emotion recognition Speech recognition Australia Task analysis Generators Speech emotion recognition self-supervised learning domain adaptation adversarial learning

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WAMP²S: Workload-Aware GPU Performance Model Based Pseudo-Preemptive Real-Time Scheduling for the Airborne embedded System

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IEEE transactions ON PARALLEL AND DISTRIBUTED systems 2022年第11期33卷 2767-2780页

作者： Yao, Yuan Liu, Shuangyang Wu, Sikai Wang, Jinyu Ni, Jinting Yang, Gang Zhang, Yu Northwestern Polytech Univ Sch Comp Sci Xian 710072 Peoples R China

New generation airborne embedded system has deployed Graphical Processing Units (GPUs) to raise processing capability to meet growing computational demands. Comparing with the cloud system, the airborne embedded system usually has a fixed application set, but strict real-time constraints. Unfortunately, the inherent GPU scheduler does not consider the application priority, which cannot provide the sufficient real-time capability to the airborne embedded system. To meet timeliness requirements, it is necessary to predict timing behaviors of those applications and design a real-time scheduling policy based on priority and deadline. We therefore propose WAMP(2)S, a workload-aware GPU performance model based pseudo-preemptive real-time scheduling algorithm for the airborne embedded system. The workload-aware GPU performance model can accurately predict the execution time of an application, which is running concurrently with other applications on GPU. The pseudo-preemptive real-time scheduling algorithm can provide the approximate preemption by dynamically adjusting GPU computing resources for active applications. Unlike previous work on GPU performance model and GPU real-time scheduling, WAMP(2)S considers the impact of co-executing workload on the execution time estimation and provides a software-only approach for preemption support. In addition, WAMP(2)S implements a prototype GPU scheduler without any source code analysis. We evaluate the proposed GPU performance model and real-time scheduling algorithm in both simulated and realistic application sets. Experimental results illustrate that WAMP(2)S can achieve low prediction error and high scheduling success ratio.

关键词： Real-time scheduling GPU performance model embedded system preemptive scheduling

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Scalable Unsupervised ML: Latency Hiding in Distributed Sparse Tensor Decomposition

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IEEE transactions ON PARALLEL AND DISTRIBUTED systems 2022年第11期33卷 3028-3040页

作者： Abubaker, Nabil Karsavuran, M. Ozan Aykanat, Cevdet Bilkent Univ Dept Comp Engn TR-06800 Ankara Turkey

Latency overhead in distributed-memory parallel CPD-ALS scales with the number of processors, limiting the scalability of computing CPD of large irregularly sparse tensors. This overhead comes in the form of sparse reduce and expand operations performed on factor-matrix rows via point-to-point messages. We propose to hide the latency overhead through embedding all of the point-to-point messages incurred by the sparse reduce and expand into dense collective operations which already exist in the CPD-ALS. The conventional parallel CPD-ALS algorithm is not amenable for embedding so we propose a computation/communication rearrangement to enable the embedding. We embed the sparse expand and reduce into a hypercube-based ALL-REDUCE operation to limit the latency overhead to O( log(2)K) for a K-processor system. The embedding comes with the cost of increased bandwidth overhead due to the multi-hop routing of factor-matrix rows during the embedded-ALL-REDUCE. We propose an embedding scheme that takes advantage of the expand/reduce properties to reduce this overhead. Furthermore, we propose a novel recursive bipartitioning framework that enables simultaneous hypergraph partitioning and subhypergraph-to-subhypercube mapping to achieve subtensor-to-processor assignment with the objective of reducing the bandwidth overhead during the embedded-ALL-REDUCE. We also propose a bin-packing-based algorithm for factor-matrix row to processor assignment aiming at reducing processors' maximum send and receive volumes during the embedded-ALL-REDUCE. Experiments on up to 4096 processors show that the proposed framework scales significantly better than the state-of-the-art point-to-point method.

关键词： Sparse tensor tensor decomposition CANDECOMP/PARAFAC canonical polyadic decomposition latency hiding embedded communication communication cost concurrent communication recursive bipartitioning hypergraph partitioning

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Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2023年第1期42卷 2-15页

作者： Najibi, Halima Levisse, Alexandre Ansaloni, Giovanni Zapater, Marina Vasic, Miroslav Atienza, David Ecole Polytech Fed Lausanne Embedded Syst Lab CH-1015 Lausanne Switzerland Univ Appl Sci Western Switzerland REDS Inst CH-2800 Delemont Switzerland Univ Politecn Madrid Ctr Elect Ind Madrid 28040 Spain

Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for 3-D multiprocessor systems-on-chip (3-D MPSoCs) realized in deeply scaled technologies, which present very challenging power and thermal requirements. Indeed, FCAs effectively improve power delivery network (PDN) performance, particularly if switched capacitor (SC) converters are employed to decouple the flow cells and the systems-on-chip voltages, allowing each to operate at their optimal point. Nonetheless, the design of FCA-based solutions entails nonobvious considerations and tradeoffs, stemming from their dual role in governing both the thermal and power delivery characteristics of 3-D MPSoCs. Showcasing them in this article, we explore multiple FCA design configurations and demonstrate that this technology can decrease the temperature of a heterogeneous 3-D MPSoC by 78 degrees C, and its total power consumption by 46%, compared to a high-performance cold-plate-based liquid cooling solution. At the same time, FCAs enable up to 90% voltage drop recovery across dies, using SC converters occupying a small fraction of the chip area. Such outcomes provide an opportunity to boost 3-D MPSoC computing performance by increasing the operating frequency of dies. Leveraging these results, we introduce a novel temperature and voltage-aware model-predictive control (MPC) strategy that optimizes power efficiency during runtime. We achieve application-wide speedups of up to 16% on various machine learning (ML), data mining, and other high-performance benchmarks while keeping the 3-D MPSoC temperature below 83 degrees C and voltage drops below 5%.

关键词： 3-D multiprocessor system-on-chip (3-MPSoC) management flow cell arrays (FCAs) model-predictive control (MPC) on-chip liquid cooling on-chip power generation online frequency optimization

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Memory-computing Decoupling: A DNN Multitasking Accelerator With Adaptive Data Arrangement

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2022年第11期41卷 4112-4123页

作者： Li, Chuxi Fan, Xiaoya Wu, Xiaoti Yang, Zhao Wang, Miao Zhang, Meng Zhang, Shengbing Northwestern Polytech Univ Sch Comp Sci Minist Educ China Engn & Res Ctr Embedded Syst Integrat Xian 710072 Peoples R China

Multiple deep neural networks (DNNs) are increasingly used in real-world intelligent applications, such as intelligent robotics and autonomous vehicles to collectively complete complicated tasks running on edge devices. Because each layer of the subtasks prefers a distinct dataflow due to the heterogeneity in shape and scale of the network layers, a variable dataflow approach on the DNN accelerators is urgently required. On DNN accelerators that enable multiple dataflows, however, we detect a dimension mismatch between parallel processing under the dataflow approach and linear data memory arrangement. When multiple DNN tasks share partial features or weights, the issue is further exacerbated. During processing, this mismatch causes a sluggish data supply from both off-chip and on-chip memory. Consequently, the overall throughput, performance, and energy efficiency suffer since DNN models are sensitive to data density. In this work, we reveal the mechanism behind this data dimension mismatch and present a series of metrics that quantify the influence on system performance. On this foundation, we offer a framework that tracks the data tensor dimension conversion and employs a flexible data arrangement over multi-DNN computation to adapt to dataflow variability. An accelerator architecture named data arrangement multi-DNN accelerator (DARMA) that features a data arrangement and distribution circuit and hierarchical memory for data dimension conversion is also presented. Since the mismatch is mitigated, the suggested accelerator outperforms current accelerators in terms of bandwidth and processing unit utilization. Through tests on VR/AR, MLperf, and other multitask applications, the evaluation results show that the proposed architecture provides both energy-efficiency and throughput improvements.

关键词： Tensors Task analysis Data models Multitasking System-on-chip Computer architecture Throughput embedded systems hardware software co-design memory modeling multiprocessor SoC scheduling

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Skills Gaps in the Industry: Opinions of embedded Software Practitioners

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ACM transactions on embedded computing systems 2021年第5期20卷 1-39页

作者： Akdur, Deniz ASELSAN Inc Ankara Turkey

Many practitioners in the software-intensive embedded industry often face difficulties after beginning their careers due to misalignment of the skills learned at the university with what is required in the workplace. Companies spend crucial resources to train personnel whose academic backgrounds are not only based on "computing disciplines" but also on non-computing ones. Analyzing the gap between the software industry and academia is important for three reasons: (1) for employers, hiring properly trained practitioners allows them to spend less time in training them while incorporating them more efficiently into the workforce;(2) for practitioners, knowing the most important skillset is helpful to increase their chance of employability;and (3) for academia, understanding the necessary skillset is critical to making curriculum changes. To achieve these objectives, we conducted a survey that yielded responses from 659 software professionals working worldwide in different roles. In this study, we only included the responses of 393 embedded software practitioners whose undergraduate degree was completed in Turkey, working in 10 countries. This article sheds light on the most important skills in the embedded software industry by presenting various cross-factor analyses. Understanding the coverage of these skills in the curriculum (mostly in Turkish universities) helps bridge the gaps, which can and should be achieved through more Industry Academia Collaborations (IACs).

关键词： Hard skills soft skills industry academia collaboration software engineering education embedded software industry practitioner survey

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Model-Based Reinforcement Learning and Neural-Network-Based Policy Compression for Spacecraft Rendezvous on Resource-Constrained embedded systems

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IEEE transactions ON INDUSTRIAL INFORMATICS 2023年第1期19卷 1107-1116页

作者： Yang, Zhibin Xing, Linquan Gu, Zonghua Xiao, Yingmin Zhou, Yong Huang, Zhiqiu Xue, Lei Nanjing Univ Aeronaut & Astronaut Sch Comp Sci & Technol Nanjing 210016 Peoples R China Umea Univ Dept Appl Phys & Elect S-90187 Umea Sweden Shanghai Aerosp Elect Technol Inst Shanghai 201100 Peoples R China

Autonomous spacecraft rendezvous is very challenging in increasingly complex space missions. In this article, we present our approach model-based reinforcement learning for spacecraft rendezvous guidance (MBRL4SRG). We build a Markov decision process model based on the Clohessy-Wiltshire equation of spacecraft dynamics and use dynamic programming to solve it and generate the decision table as the optimal agent policy. Since the onboard computing system of spacecraft is resource constrained in terms of both memory size and processing speed, we train a neural network (NN) as a compact and efficient function approximation to the tabular representation of the decision table. The NN outputs are formally verified using the verification tool ReluVal, and the verification results show that the robustness of the NN is maintained. Experimental results indicate that MBRL4SRG achieves lower computational overhead than the conventional proportional-integral-derivative algorithm and has higher trustworthiness and better computational efficiency during training than the model-free reinforcement learning algorithms.

关键词： Space vehicles Artificial neural networks Mathematical models Vehicle dynamics Reinforcement learning Predictive models Computational modeling Formal verification Markov decision process (MDP) model-based reinforcement learning spacecraft rendezvous guidance

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