检索结果-内蒙古大学图书馆

Adversarial Transferability in embedded Sensor systems: An Activity Recognition Perspective

ACM transactions on embedded computing systems 2024年第2期23卷 1-31页

作者： Sah, Ramesh Kumar Ghasemzadeh, Hassan Washington State Univ POB 641035 Pullman Pullman WA 99164 USA Arizona State Univ 1151 S Forest Ave Tempe AZ 85281 USA

Machine learning algorithms are increasingly used for inference and decision-making in embedded systems. Data from sensors are used to train machine learning models for various smart functions of embedded and cyber-physical systems ranging from applications in healthcare, autonomous vehicles, and national security. However, recent studies have shown that machine learning models can be fooled by adding adversarial noise to their inputs. The perturbed inputs are called adversarial examples. Furthermore, adversarial examples designed to fool one machine learning system are also often effective against another system. This property of adversarial examples is called adversarial transferability and has not been explored in wearable systems to date. In this work, we take the first stride in studying adversarial transferability in wearable sensor systems from four viewpoints: (1) transferability between machine learning models;(2) transferability across users/subjects of the embedded system;(3) transferability across sensor body locations;and (4) transferability across datasets used for model training. We present a set of carefully designed experiments to investigate these transferability scenarios. We also propose a threat model describing the interactions of an adversary with the source and target sensor systems in different transferability settings. In most cases, we found high untargeted transferability, whereas targeted transferability success scores varied from 0% to 80%. The transferability of adversarial examples depends on many factors such as the inclusion of data from all subjects, sensor body position, number of samples in the dataset, type of learning algorithm, and the distribution of source and target system dataset. The transferability of adversarial examples decreased sharply when the data distribution of the source and target system became more distinct. We also provide guidelines and suggestions for the community for designing robust sensor systems. Code

关键词： Sensor systems human activity recognition adversarial machine learning adversarial transferability

来源：评论

学校读者我要写书评

暂无评论

AXI Hardware Accelerator for McEliece on FPGA embedded systems

引用

IEEE transactions ON DEPENDABLE AND SECURE computing 2025年第2期22卷 1477-1490页

作者： Canto-Navarro, Enrique Lopez-Garcia, Mariano Univ Rovira I Virgili Elect Elect & Automatic Dept Tarragona 43007 Spain Univ Politecn Cataluna Dept Elect Vilanova I La Geltru 08800 Spain

This article presents a McEliece hardware accelerator designed to be attached to an AXI infrastructure, addressing the efficient implementation of a flexible post-quantum cryptoprocessor on FPGA-based embedded systems. The complexity of the arithmetic circuits, combined with the adaptability to different applications by configurable parameters and run-time reprogramming, presents challenging issues for integrating the accelerator into these systems. The architecture of the accelerator is based on an application-specific instruction processor, which executes a set of constant-time instructions from an internal register file and memories. The role of the embedded processor is reduced to the initial writing of the instruction memory of the accelerator, the launching of the required set of instructions and configuring the Direct Memory Access controller to retrieve and store data from external memory. The run-time programming of the accelerator provides high flexibility in applications that requires post-quantum cryptography. A set of configurable parameters permits to adapt the security level of the McEliece encryption-decryption and the area-performance tradeoff imposed by the target device. Thus, the accelerator can be implemented from low-cost to high-end FPGAs by configuring the data-width of DMA buses or the parallelism level of the Galois-Field adder-multiplier. Experimental results show the accelerator is suited for implementing efficiently the highest security parameters of the Classic McEliece, achieving a McEliece decryption speed-up from x370 to x556 and occupying a small number of resources on a low-cost FPGA. In high-end FPGAs, the accelerator can be configured using higher security parameters not achieved in previous related cryptoprocessors, providing even higher accelerations.

关键词： Field programmable gate arrays Cryptography Clocks Codes Microprocessors Table lookup Encryption Public key cryptosystem real-time and embedded systems reconfigurable hardware

来源：评论

学校读者我要写书评

暂无评论

Kryptonite : Worst-Case Program Interference Estimation on Multi-Core embedded systems

引用

ACM transactions on embedded computing systems 2023年第5期22卷 1-23页

作者： Singh, Nikhilesh Renganathan, Karthikeyan Rebeiro, Chester Jose, Jithin Mader, Ralph IIT Madras SAFE Lab Chennai Tamil Nadu India Vitesco Technol Bengaluru Karnataka India Vitesco Technol Regensburg Germany

Due to the low costs and energy needed, cyber-physical systems are adopting multi-core processors for their embedded computing requirements. In order to guarantee safety when the application has real-time constraints, a critical requirement is to estimate the worst-case interference from other executing programs. However, the complexity of multi-core hardware inhibits precisely determining the Worst-Case Program Interference. Existing solutions are either prone to overestimate the interference or are not scalable to different hardware sizes and designs. In this paper we present Kryptonite, an automated framework to synthesize Worst-Case Program Interference (WCPI) environments for multi-core systems. Fundamental to Kryptonite is a set of tiny hardware-specific code gadgets that are crafted to maximize interference locally. The gadgets are arranged using a greedy approach and then molded using a Reinforcement Learning algorithm to create the WCPI environment. We demonstrate Kryptonite on the automotive grade Infineon AURIX TC399 processor with a wide range of programs that includes a commercial real-time automotive application. We show that, while being easily scalable and tunable, Kryptonite creates WCPI environments increasing the runtime by up to 58% for benchmark applications and 26% for the automotive application.

关键词： Program interference worst-case analysis

来源：评论

学校读者我要写书评

暂无评论

Design and Analysis of a Closed-Loop Emotion Regulation System Based on Multimodal Affective computing and Emotional Markov Chain

引用

IEEE transactions ON systems MAN CYBERNETICS-systems 2025年第4期55卷 2426-2437页

作者： Wang, Xingchao Li, Chen-Zhong Sun, Zhenglong Xu, Yangsheng Chinese Univ Hong Kong Shenzhen Inst Artificial Intelligence & Robot Soc Shenzhen 518172 Guangdong Peoples R China Chinese Univ Hong Kong Sch Med Biooptoelect & Biosensors Lab Shenzhen 518172 Guangdong Peoples R China Chinese Univ Hong Kong Sch Sci & Engn Shenzhen 518172 Guangdong Peoples R China

In our daily lives, emotions are extremely important. However, predicting and regulating emotion is still a critical problem to be solved in the research of the human-computer interaction (HCI). In this study, we explore this problem using a regulation method. A novel multimodal affective computing algorithm is proposed and implemented in an emotion regulation system. The selection of music stimuli and the modeling of dynamic emotions are done using emotional Markov chains. This regulation system can monitor the user's emotion and play music, selected by the regulation policy until the user can maintain the desired emotion. Our system was verified by two experiments. In the first experiment, by predicting the participants' affective states, we tested the precision of our multimodal affective computing system. In the second experiment, we tested the regulation algorithm embedded in a closed-loop regulation system by comparing it with playing music without feedback. The results suggest that participants can regulate and maintain the desired affective state by using the emotion regulation system.

关键词： Affective computing emotion regulation emotional Markov chain human-computer interaction (HCI) Affective computing emotion regulation emotional Markov chain human-computer interaction (HCI)

来源：评论

学校读者我要写书评

暂无评论

AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling

引用

IEEE transactions ON CIRCUITS AND systems I-REGULAR PAPERS 2024年第6期71卷 2646-2659页

作者： Sahoo, Siva Satyendra Ullah, Salim Bhattacharjee, Soumyo Kumar, Akash IMEC B-3001 Leuven Belgium Ruhr Univ Bochum Chair Embedded Syst D-44801 Bochum Germany Swiss Fed Inst Technol Dept Informat Technol & Elect Engn ITET CH-8006 Zurich Switzerland

The rising usage of AI/ML-based processing across application domains has exacerbated the need for low-cost ML implementation, specifically for resource-constrained embedded systems. To this end, approximate computing, an approach that explores the power, performance, area (PPA), and behavioral accuracy (BEHAV) trade-offs, has emerged as a possible solution for implementing embedded machine learning. Due to the predominance of MAC operations in ML, designing platform-specific approximate arithmetic operators forms one of the major research problems in approximate computing. Recently, there has been a rising usage of AI/ML-based design space exploration techniques for implementing approximate operators. However, most of these approaches are limited to using ML-based surrogate functions for predicting the PPA and BEHAV impact of a set of related design decisions. While this approach leverages the regression capabilities of ML methods, it does not exploit the more advanced approaches in ML. To this end, we propose, a methodology for designing approximate arithmetic operators through ML-based supersampling. Specifically, we present a method to leverage the correlation of PPA and BEHAV metrics across operators of varying bit-widths for generating larger bit-width operators. The proposed approach involves traversing the relatively smaller design space of smaller bit-width operators and employing its associated Design-PPA-BEHAV relationship to generate initial solutions for metaheuristics-based optimization for larger operators. The experimental evaluation of for FPGA-optimized approximate operators shows that the proposed approach significantly improves the quality-resulting hypervolume for multi-objective optimization-of 8 x 8 signed approximate multipliers.

关键词： AI-based design space exploration approximate computing arithmetic operator design circuit synthesis

来源：评论

学校读者我要写书评

暂无评论

MCAM: Memductance Components Adaptive Model for Efficient Modeling of Memductance of Memristive Devices for Neuromorphic Circuits and systems

引用

IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第10期43卷 2958-2971页

作者： Sichani, Ali Shiri Moreno, Wilfrido A. Univ Missouri Dept Elect Engn & Comp Sci Columbia MO 65211 USA Univ S Florida Dept Elect Engn Tampa FL 33620 USA

As an emerging technology, memristive devices have flourished to develop energy-efficient computing systems in the form of emerging nonvolatile memories (eNVMs), synaptic connections, and logic design, which could play a critical role in microelectronic design. In neuromorphic applications, the power-off state of a nonvolatile memristor is crucial, as it determines the learning and forgetting of embedded synaptic efficacy. Due to the complexity of the transport mechanisms contributing to the memristor current, memristor modeling remains a critical challenge. The memductance of memristors includes both volatile and nonvolatile components, which can be modeled using a memductance components adaptive model (MCAM). The MCAM enables researchers to model the memductance of memristors, which can be used in neuromorphic applications and logic design. Mathematical explanations and two physical models of memristors extracted from experimental results demonstrate the model's accuracy. The application of MCAM for synaptic updates in spiking neuromorphic systems is also shown.

关键词： Memristors Computational modeling Neuromorphics Mathematical models Nonvolatile memory Switches Integrated circuit modeling Memductance memristor neuromorphic computing nonvolatile memories synaptic efficacy

来源：评论

学校读者我要写书评

暂无评论

FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in embedded systems

引用

IEEE transactions ON COMPUTERS 2025年第1期74卷 71-85页

作者： Li, Jingjin Jiang, Weixiong He, Yuting Yang, Qingyu Gao, Anqi Ha, Yajun Ozcan, Ender Bai, Ruibin Cui, Tianxiang Yu, Heng Univ Nottingham Ningbo China Sch Comp Sci Ningbo 315100 Peoples R China ShanghaiTech Univ Sch Informat Sci & Technol Shanghai 201210 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 101408 Peoples R China ShanghaiTech Univ Shanghai Engn Res Ctr Energy Efficient & Custom AI Shanghai 201210 Peoples R China Univ Nottingham Sch Comp Sci Nottingham NG8 1BB England

Deep Reinforcement Learning (DRL)-based Dynamic Voltage Frequency Scaling (DVFS) has shown great promise for energy conservation in embedded systems. While many works were devoted to validating its efficacy or improving its performance, few discuss the feasibility of the DRL agent deployment for embedded computing. State-of-the-art approaches focus on the miniaturization of agents' inferential networks, such as pruning and quantization, to minimize their energy and resource consumption. However, this spatial-based paradigm still proves inadequate for resource-stringent systems. In this paper, we address the feasibility from a temporal perspective, where FiDRL, a flexible invocation-based DRL model is proposed to judiciously invoke itself to minimize the overall system energy consumption, given that the DRL agent incurs non-negligible energy overhead during invocations. Our approach is three-fold: (1) FiDRL that extends DRL by incorporating the agent's invocation interval into the action space to achieve invocation flexibility;(2) a FiDRL-based DVFS approach for both inter- and intra-task scheduling that minimizes the overall execution energy consumption;and (3) a FiDRL-based DVFS platform design and an on/off-chip hybrid algorithm specialized for training the DRL agent for embedded systems. Experiment results show that FiDRL achieves 55.1% agent invocation cost reduction, under 23.3% overall energy reduction, compared to state-of-the-art approaches.

关键词： Training Energy consumption Costs Scheduling Optimization Vectors System-on-chip Deep reinforcement learning DVFS lightweight AI energy optimization

来源：评论

学校读者我要写书评

暂无评论

Workload-Aware Performance Model Based Soft Preemptive Real-Time Scheduling for Neural Processing Units

引用

IEEE transactions ON PARALLEL AND DISTRIBUTED systems 2025年第6期36卷 1058-1070页

作者： Yao, Yuan Hu, Yujiao Dang, Yi Tao, Wei Hu, Kai Huang, Qiming Peng, Zhe Yang, Gang Zhou, Xingshe Northwestern Polytech Univ Sch Comp Sci Xian 710072 Peoples R China Future Network Res Ctr Purple Mt Labs Nanjing 211111 Peoples R China Hong Kong Polytech Univ Dept Ind & Syst Engn Hong Kong Peoples R China Hong Kong Polytech Univ Shenzhen Res Inst Shenzhen 518055 Peoples R China

A neural processing unit (NPU) is a microprocessor which is specially designed for various types of neural network applications. Because of its high acceleration efficiency and lower power consumption, the airborne embedded system has widely deployed NPU to replace GPU as the new accelerator. Unfortunately, the inherent scheduler of NPU does not consider real-time scheduling. Therefore, it cannot meet real-time requirements of airborne embedded systems. At present, there is less research on the multi-task real-time scheduling of the NPU device. In this article, we first design an NPU resource management framework based on Kubernetes. Then, we propose WAMSPRES, a workload-aware NPU performance model based soft preemptive real-time scheduling method. The proposed workload-aware NPU performance model can accurately predict the remaining execution time of the task when it runs with other tasks concurrently. The soft preemptive real-time scheduling algorithm can provide approximate preemption capability by dynamically adjusting the NPU computing resources of tasks. Finally, we implement a prototype NPU scheduler of the airborne embedded system for the fixed-wing UAV. The proposed models and algorithms are validated on both the simulated and realistic task sets. Experimental results illustrate that WAMSPRES can achieve low prediction error and high scheduling success rate.

关键词： Graphics processing units Real-time systems embedded systems Computational modeling Resource management Adaptation models Kernel Computer architecture Atmospheric modeling Performance evaluation embedded system soft preemptive scheduling real-time scheduling computing power dynamic-quota NPU performance model

来源：评论

学校读者我要写书评

暂无评论

Implementation of Adaptive Partial Discharge Denoising in Resource-Limited embedded systems via Efficient Time-Frequency Matrix Factorization

引用

IEEE transactions ON INSTRUMENTATION AND MEASUREMENT 2024年 73卷 1页

作者： Yan, Yuan Trinchero, Riccardo Stievano, Igor Simone Li, Hongjie Xi An Jiao Tong Univ Sch Elect Engn State Key Lab Insulat & Power Equipment Xian 710049 Peoples R China Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy Xi An Jiao Tong Univ Sch Elect Engn State Key Lab Insulat & Power Equipment Xian 710049 Peoples R China

As low-cost Internet-of-Things (IoT)-based partial discharge (PD) monitors for medium-voltage apparatuses in distribution power systems increase, developing an effective PD denoising algorithm is crucial to improve their robustness to on-site noise. Yet, denoising PD signals in the monitoring devices is challenging primarily due to three critical reasons, i.e., high-level field noises, uncertain PD waveforms, and limited computing resources. This work describes an adaptive and efficient PD denoising algorithm based on the improved spectral decomposition of the noisy PD signal. PD pulses are accurately extracted from the noisy signal by selecting the dominant components via a low-rank singular value decomposition (SVD) of the time-frequency spectrogram of the signal, thus reducing the size of the involved matrices and the computational complexity. The performance of the proposed denoising algorithm is first demonstrated on a synthetic PD signal and compared with state-of-the-art alternatives implemented on three embedded systems commonly used for PD monitoring. Finally, the strength and the effectiveness of the proposed approach are further validated on experimental data based on the measurement of IoT-based PD monitors for 35-kV switchgears.

关键词： embedded systems kurtosis criteria partialdischarge (PD) denoising randomized singular value decomposition (SVD) short-time Fourier transform (STFT)

来源：评论

学校读者我要写书评

暂无评论

NICE: A Nonintrusive In-Storage-computing Framework for embedded Applications

引用

IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2024年第11期43卷 3876-3887页

作者： Wang, Tianyu Zhu, Yongbiao Li, Shaoqi Xue, Jin Ma, Chenlin Wang, Yi Shen, Zhaoyan Shao, Zili Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen 518060 Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Peoples R China Shandong Univ Sch Comp Sci & Technol Qingdao 266237 Peoples R China Huazhong Univ Sci & Technol Wuhan Natl Lab Optoelect Wuhan 430074 Peoples R China

embedded machine learning applications face challenges related to massive data movement and high computational intensity, exacerbated by the limited performance of mobile devices. Computational storage devices (CSDs) pose huge potential for accelerating both data-intensive and computation-intensive embedded machine learning tasks by effectively reducing data movement and leveraging built-in accelerators. However, existing in-storage-computing (ISC) frameworks either require invasive customization of existing host driver layers or necessitate complex device firmware modifications, hindering the widespread deployment of CSDs. In addition, the lack of file semantics and the constrained internal resources within CSD implicitly compromise system performance and impact normal read/write performance. In this article, we aim to provide a nonintrusive in-storage-computing framework for embedded applications, named NICE. This framework includes an easy-to-use ISC programming interface that bypasses the kernel stack and requires no modification to the host NVMe driver, which is achieved through a novel hyper-addressing-based programming library and a file-aware page data layout within the CSD. In addition, we incorporate a lightweight kernel with coroutine-based command scheduling and several FPGA-based accelerators within the storage device firmware to enhance the performance of embedded machine learning applications while ensuring that the normal I/O performance remains unaffected. NICE is implemented on real CSD hardware integrated with ARM and FPGA. Experimental results demonstrate that our NICE framework can achieve an average latency performance improvement of $43.5\times $ ( $9.32\times $ ) compared to CPU-(GPU-) based embedded machine learning solutions using the state-of-the-art NVIDIA Jetson NX platform, with $27.5\times $ ( $4.3\times $ ) higher energy efficiency. NICE also has $34.2\times $ less software and I/O performance overheads than state-of-the-art ISC frame

关键词： Task analysis Microprogramming Field programmable gate arrays Machine learning Performance evaluation Kernel Vectors Computational storage device (CSD) embedded system in storage computing (ISC) solid state drive

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：