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SenHDC: A 3-D NAND Flash-Based Processing-in-Sensor Hyperdimensional computing Architecture

IEEE transactions ON VERY LARGE SCALE INTEGRATION (VLSI) systems 2025年

作者： Huang, Xuchu Huang, Qingrong Yang, Zeyu Zhou, Min Yan, Zheyu Zhuo, Cheng Yin, Xunzhao Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China Zhejiang Univ Inst Translat Med Hangzhou 310058 Peoples R China Zhejiang Univ Sch Integrated Circuits Hangzhou 310000 Peoples R China Zhejiang Univ Key Lab Collaborat Sensing & Autonomous Unmanned S Hangzhou 310000 Peoples R China Key Lab CS & AUS Zhejiang Prov Hangzhou 310027 Peoples R China

The rapid growth of the Internet of Things (IoT) promotes vision application deployments in embedded devices. To alleviate the data conversion and transmission overheads in CMOS image sensor (CIS), processing-in-sensor (PIS) has been proposed, enabling computations to occur directly within sensory systems. Meanwhile, brain-inspired hyperdimensional computing (HDC) emerges as a promising computing paradigm well-suited for PIS due to its high accuracy and efficiency in various cognitive tasks. However, HDC requires transforming the sensed signals into long hypervectors (HVs), which imposes significant overhead for PIS systems. Thus, in this article, we propose SenHDC, a hardware-software co-design framework for HDC-based PIS. We introduce a novel hardware-friendly encoding paradigm that eliminates complex HV transformations, coupled with a noise-resilient position HV generation method that mitigates the impact of capacitance load imbalance. We further present an efficient 3-D NAND flash-based compute-in-memory (CIM) hardware design, comprising an encoding module that performs encoding in charge domain and an associative search module that checks the similarity between the input and prestored classes for classification. Experimental results show that SenHDC improves energy efficiency by 40.6x and 1.6x in the encoding module and associative search module, respectively, compared to the state-of-the-art HDC CIM implementations.

关键词： Encoding Three-dimensional displays In-memory computing Hardware Computer architecture Training Flash memories Energy efficiency Common Information Model (computing) Virtual machine monitors computing-in-memory flash memory hyperdimensional computing (HDC)

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Thermal Management for 3D-Stacked systems via Unified Core-Memory Power Regulation

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ACM transactions on embedded computing systems 2023年第5期22卷 1-26页

作者： Shen, Yixian Schreuders, Leo Pathania, Anuj Pimentel, Andy D. Univ Amsterdam Sci Pk 900 NL-1098 XH Amsterdam Netherlands

3D-stacked processor-memory systems stack memory (DRAM banks) directly on top of logic (CPU cores) using chiplet-on-chiplet packaging technology to provide the next-level computing performance in embedded platforms. Stacking, however, severely increases the system's power density without any accompanying increase in the heat dissipation capacity. Consequently, 3D-stacked processor-memory systems suffer more severe thermal issues than their non-stacked counterparts. Nevertheless, 3D-stacked processor-memory systems do inherit power (thermal) management knobs from their non-stacked predecessors - namely Dynamic Voltage and Frequency Scaling (DVFS) for cores and Low Power Mode (LPM) for memory banks. In the context of 3D-stacked processor-memory systems, DVFS and LPM are performance- and power-wise deeply intertwined. Their non-unified independent use on 3D-stacked processor-memory systems results in suboptimal thermal management. The unified use of DVFS and LPM for thermal management for 3D-stacked processor-memory systems remains unexplored. The lack of implementation of LPM in thermal simulators for 3D-stacked processor-memory systems hinders real-world representative evaluation for a unified approach. We extend the state-of-the-art interval thermal simulator for 3D-stacked processor-memory systems CoMeT with an LPM power management knob for memory banks. We also propose a learning-based thermal management technique for 3D-stacked processor-memory systems that employ DVFS and LPM in a unified manner. Detailed interval thermal simulations with the extended CoMeT framework show a 10.15% average response time improvement with the PARSEC and SPLASH-2 benchmark suites, along with widely-used Deep Neural Network (DNN) workloads against a state-of-the-art thermal management technique for 2.5D processor-memory systems (ported directly to 3D-stacked processor-memory systems) that also proposes unified use of DVFS and LPM.

关键词： Low power design resource-constrained edge computing embedded systems 3D-stacked processors AI for systems chiplet-on-chiplet stacking

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HEXO: Offloading Long-Running Compute- and Memory-Intensive Workloads on Low-Cost, Low-Power embedded systems

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IEEE transactions ON CLOUD computing 2024年第4期12卷 1415-1432页

作者： Olivier, Pierre Mehrab, A. K. M. Fazla Errabelly, Sandeep Lankes, Stefan Karaoui, Mohamed Lamine Lyerly, Robert Kim, Sang-Hoon Barbalace, Antonio Ravindran, Binoy Univ Manchester Dept Comp Sci Manchester M13 9PL England Virginia Tech Blacksburg VA 24061 USA Virginia Tech Syst Software Res Grp Blacksburg VA 24061 USA Rhein Westfal TH Aachen Inst Automat Complex Power Syst D-52062 Aachen Germany Huawei F-92100 Boulogne Billancourt France Ajou Univ Suwon 16499 South Korea Univ Edinburgh Sch Informat Edinburgh EH8 9YL Scotland

OS-capable embedded systems exhibiting a very low power consumption are available at an extremely low price point. It makes them highly compelling in a datacenter context. We show that sharing long-running, compute-intensive datacenter workloads between a server machine and one or a few connected embedded boards of negligible cost and power consumption can yield significant performance and energy benefits. Our approach, named Heterogeneous EXecution Offloading (HEXO), selectively offloads Virtual Machines (VMs) from server-class machines to embedded boards. Our design tackles several challenges. We address the Instruction Set Architecture (ISA) difference between typical servers (x86) and embedded systems (ARM) through hypervisor and guest OS-level support for heterogeneous-ISA runtime VM migration. We cope with the low amount of resources in embedded systems by using lightweight VMs - unikernels - and by using the server's free RAM as remote memory for embedded boards through a transparent lightweight memory disaggregation mechanism for heterogeneous server-embedded clusters, called Netswap. VMs are offloaded based on an estimation of the slowdown expected from running on a given board. We build a prototype of HEXO and demonstrate significant increases in throughput (up to 67%) and energy efficiency (up to 56%) using benchmarks representative of compute-intensive long-running workloads.

关键词： Servers embedded systems Benchmark testing Power demand Costs Memory management Throughput Random access memory Linux Virtual machine monitors Heterogeneous ISAs unikernels migration offloading

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SMaLL: Software for Rapidly Instantiating Machine Learning Libraries

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ACM transactions on embedded computing systems 2024年第3期23卷 1-25页

作者： Sridhar, Upasana Tukanov, Nicholai Binder, Elliott Low, Tze Meng McMllan, Scott Schatz, Martin D. Carnegie Mellon Univ 5000 Forbes Ave Pittsburgh PA 15213 USA Carnegie Mellon Univ Inst Software Engn 4500 Fifth Ave Pittsburgh PA 15213 USA Meta 1 Hacker Way Menlo Pk CA 94025 USA

Interest in deploying deep neural network (DNN) inference on edge devices has resulted in an explosion of the number and types of hardware platforms that machine learning (ML) libraries must support. High-level programming interfaces, such as TensorFlow, can be readily ported across different devices;however, maintaining performance when porting the low-level implementation is more nuanced. High-performance inference implementations require an effective mapping of the high-level interface to the target hardware platform. Commonly, this mapping may use optimizing compilers to generate code at compile time or high-performance vendor libraries that have been specialized to the target platform. Both approaches rely on expert knowledge across levels to produce an efficient mapping. This makes supporting new architectures difficult and time-consuming. In this work, we present a DNN library framework, SMaLL, that is easily extensible to new architectures. The framework uses a unified loop structure and shared, cache-friendly data format across all intermediate layers, eliminating the time and memory overheads incurred by data transformation between layers. Each layer is implemented by specifying its dimensions and a kernel, the key computing operation of that layer. The unified loop structure and kernel abstraction allows the reuse of code across layers and computing platforms. New architectures only require a few hundred lines in the kernel to be redesigned. To show the benefits of our approach, we have developed software that supports a range of layer types and computing platforms;this software is easily extensible for rapidly instantiating high-performance DNN libraries. An evaluation of the portability of our framework is shown by instantiating end-to-end networks from the MLPerf:tiny benchmark suite on five ARM platforms and one x86 platform (an AMD Zen 2). We also show that the end-to-end performance is comparable to or better than ML frameworks such as TensorFlow, T

关键词： Mathematical software machine learning libraries high-performance portability embedded systems

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Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on systems Containing In-Memory computing Units

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IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2023年第11期42卷 3757-3767页

作者： Mambu, Kevin Charles, Henri-Pierre Kooli, Maha Univ Grenoble Alpes CEA LIST F-38000 Grenoble France

In memory computing (IMC) aims at solving the performance gap between CPU and memories introduced by the memory wall. However, general-purpose IMC does not consider the optimization of data transfers for patterns, such as stencils and convolutions. This article proposes a new instruction set architecture (ISA) and a novel pattern encoding for IMC to transfer and organize data streams in order to perform efficiently computation. This instruction set is implemented on the data-locality management unit (DMU) as a subset of the computational SRAM (C-SRAM) ISA. A programming model to interact with the DMU at language level is also presented in this article. This DMU ISA is evaluated on six applications run on three different system nodes. These system nodes are based on existing RISC-V cores and range from embedded to high-performance computing domain. Experiments show on average a speed-up of x8.81, an energy reduction factor of x6.81, and an improvement of the number of operations per cycle of x4.59, for the C-SRAM architecture integrating the proposed ISA of the DMU compared to a reference implementation on embedded systems. Results also show an improvement of the number of operations per cycle of x2.99 compared to a reference implementation on all system nodes.

关键词： Computer architecture Instruction sets Random access memory Programming Computational modeling Central Processing Unit Data transfer Convolution in-memory computing (IMC) instruction set architecture (ISA) non-von Neumann pattern performance analysis programming model stencil

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RAD-FS: Remote Timing and Power SCA Security in DVFS-augmented Ultra-Low-Power embedded systems

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ACM transactions on embedded computing systems 2025年第2期24卷 1-27页

作者： Dobkin, Daniel Cever, Nimrod Levi, Itamar Bar Ilan Univ Fac Engn Ramat Gan Israel

High-performance crypto-engines have become crucial components in modern System-On-Chip (SoC) architectures across platforms, from servers to edge-IoTs'. Alas, their secure operation faces a significant obstacle caused by information-leakage accessed through Side-Channel Analysis (SCA). Adversaries exploit statistical-analysis techniques on measured (e.g.,) power and timing signatures generated during (e.g.,) encryption, extracting secrets. Mathematical countermeasures against such attacks often impose substantial power-performance-area overheads. Dynamic Voltage and Frequency Scaling (DVFS) techniques provide power-efficiency by varying power consumption according to workload;these modulations are called power-states. Unintentionally, DVFS introduces new inherent weaknesses exploitable by malicious actors: power-states leak information in both power and timing side-channels, measurable in software and hardware. We introduce a method to increase side-channel resistance using integrated voltage regulators and DVFS: (1) Pushing known prior-art in the topic to Ultra Low Power (ULP) regime (2) For the first time introducing a mechanism to aid in counteracting the inherent weakness of DVFS in SCA (3) Providing measurements performed on 40 nm process ULP PLS15 test-chip down at 580 mV power-supply (4) Offering improved and parameterized resistance to remote-timing vulnerabilities inherent to DVFS. We present various results and perform a detailed analysis while comparing performance and security to prior-art. Importantly, our solution is configurable in terms of security, maintaining degrees-of-freedom for power-optimization of DVFS.

关键词： DVFS Template attack Hertzbleed timing attack

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Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based embedded System

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ACM transactions on embedded computing systems 2025年第1期24卷 1-32页

作者： Chang, Liangliang Gener, Serhan Mack, Joshua Suluhan, Hasan umut Akoglu, Ali Chakrabarti, Chaitali Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85281 USA Univ Arizona Elect & Comp Engn Dept Tucson AZ USA

In this study, we introduce a methodology for automatically transforming user applications written in C/C++ to a parallel representation consisting of coarse-grained tasks based on dynamic profiling. Such a parallel representation is suitable for mapping applications onto heterogeneous SoCs. We present our approach for instrumenting the user application binary during the compilation process with parallel primitives that enable the runtime system to schedule and execute independent computation-intensive coarse-grained tasks concurrently. We use the proposed compilation and code transformation methodology to retarget each application for execution on a heterogeneous SoC composed of processor cores and accelerators. We demonstrate the capabilities of our integrated compile time and runtime flow through task-level parallelization and functionally correct execution of real-world applications in the communication systems and radar processing domains. We demonstrate the functionality of our integrated system by executing six distinct applications with different degrees of parallelism on four different platforms: an eight-core general-purpose processor, a heterogeneous SoC simulator, and two heterogeneous SoCs utilizing the Xilinx Zynq UltraScale+ FPGA and the Nvidia Jetson AGX board. Our integrated approach offers a path forward for application developers to take full advantage of the target SoC without requiring users to become hardware or parallel programming experts.

关键词： Coarse-grained task parallelization dynamic profiling heterogeneous SoC and runtime parallelism detection

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Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

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ACM transactions ON ARCHITECTURE AND CODE OPTIMIZATION 2024年第3期21卷 1-23页

作者： Li, Qunyou Huang, Darong Costero, Luis Zapater, Marina Atienza, David Ecole Polytech Fed Lausanne EPFL Embedded Syst Lab ESL Lausanne Switzerland Univ Complutense Madrid Dept Comp Architecture & Automat Madrid Spain Univ Appl Sci Western Switzerland HES SO Inst Reconfigurable & Embedded Digital Syst REDS Sch Engn & Management Vaud Yverdon Switzerland

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use of Accelerated Processing Units (APUs), processors that incorporate both a central processing unit (CPU) and an integrated graphics processing unit (iGPU). However, the performance of both APU and CPU systems can be significantly hampered by address translation overhead, leading to a decline in overall performance, especially for cache-resident workloads. To address this issue, we propose the introduction of a new intermediate address space (IAS) in both APU and CPU systems. IAS serves as a bridge between virtual address (VA) spaces and physical address (PA) spaces, optimizing the address translation process. In the case of APU systems, our research indicates that the iGPU suffers from significant translation look-aside buffer (TLB) misses in certain workload situations. Using an IAS, we can divide the initial address translation into front- and back-end phases, effectively shifting the bottleneck in address translation from the cache side to the memory controller side, a technique that proves to be effective for cache-resident workloads. Our simulations demonstrate that implementing IAS in the CPU system can boost performance by up to 40% compared to conventional CPU systems. Furthermore, we evaluate the effectiveness of APU systems, comparing the performance of IAS-based systems with traditional systems, showing up to a 185% improvement in APU system performance with our proposed IAS implementation. Furthermore, our analysis indicates that over 90% of TLB misses can be filtered by the cache, and employing a larger cache within the system could potentially result in even greater improvements. The proposed IAS offers a promising and practical solution to enhance the performance of both APU and CPU systems, contrib

关键词： Computer architecture CPU GPU virtual memory TLB cache

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PUF for the Commons: Enhancing embedded Security on the OS Level

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IEEE transactions ON DEPENDABLE AND SECURE computing 2024年第4期21卷 2194-2210页

作者： Kietzmann, Peter Schmidt, Thomas C. Wahlisch, Matthias HAW Hamburg Dept Informat D-20099 Hamburg Germany Tech Univ Dresden Fac Comp Sci D-01069 Dresden Germany Barkhausen Inst D-01187 Dresden Germany

Security is essential for the Internet of Things (IoT). Cryptographic operations for authentication and encryption commonly rely on random input of high entropy and secure, tamper-resistant identities, which are difficult to obtain on constrained embedded devices. In this paper, we design and analyze a generic integration of physically unclonable functions (PUFs) into the IoT operating system RIOT that supports about 250 platforms. Our approach leverages uninitialized SRAM to act as the digital fingerprint for heterogeneous devices. We ground our design on an extensive study of PUF performance in the wild, which involves SRAM measurements on more than 700 IoT nodes that aged naturally in the real-world. We quantify static SRAM bias, as well as the aging effects of devices and incorporate the results in our system. This work closes a previously identified gap of missing statistically significant sample sizes for testing the unpredictability of PUFs. Our experiments on COTS devices of 64 kB SRAM indicate that secure random seeds derived from the SRAM PUF provide 256 Bits-, and device unique keys provide more than 128 Bits of security. In a practical security assessment we show that SRAM PUFs resist moderate attack scenarios, which greatly improves the security of low-end IoT devices.

关键词： Physical unclonable function Physically unclonable functions embedded security large-scale SRAM analysis operating systems Physical unclonable function Physically unclonable functions embedded security large-scale SRAM analysis operating systems

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Energy-Efficient, Delay-Constrained Edge computing of a Network of DNNs

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IEEE transactions ON COMPUTERS 2025年第2期74卷 569-581页

作者： Ghasemi, Mehdi Heidari, Soroush Kim, Young Geun Wu, Carole-Jean Vrudhula, Sarma Arizona State Univ Tempe AZ 85281 USA Korea Univ Seoul 02841 South Korea Meta Inc Cambridge MA 02142 USA

This paper presents a novel approach for executing the inference of a network of pre-trained deep neural networks (DNNs) on commercial-off-the-shelf devices that are deployed at the edge. The problem is to partition the computation of the DNNs between an energy-constrained and performance-limited edge device EE, and an energy-unconstrained, higher performance device CC, referred to as the cloudlet, with the objective of minimizing the energy consumption of EE subject to a deadline constraint. The proposed partitioning algorithm takes into account the performance profiles of executing DNNs on the devices, the power consumption profiles, and the variability in the delay of the wireless channel. The algorithm is demonstrated on a platform that consists of an NVIDIA Jetson Nano as the edge device EE and a Dell workstation with a Titan Xp GPU as the cloudlet. Experimental results show significant improvements both in terms of energy consumption of EE and processing delay of the application. Additionally, it is shown how the energy-optimal solution is changed when the deadline constraint is altered. Moreover, the overhead of decision-making for our proposed method is significantly lower than the state-of-the-art Integer Linear Programming (ILP) solutions.

关键词： Flow graphs Performance evaluation Delays Computational modeling Servers Artificial neural networks Energy efficiency Energy consumption Data models Image edge detection Deep neural networks IoT edge energy efficiency

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