检索结果-内蒙古大学图书馆

IEEE transactions on Artificial Intelligence 2024年第10期5卷 4928-4937页

作者： Rafiei, Hamed Akbarzadeh-T, Mohammad-R Ferdowsi University of Mashhad Department of Electrical Engineering Center of Excellence on Soft Computing and Intelligent Information Processing Mashhad*** Iran Chalmers University of Technology Department of Electrical Engineering Center for Bionics and Pain Research Mölndal Gothenburg412 96 Sweden

In the realm of natural language processing, hedge-embedded structures have contributed considerably by appreciating linguistic variables and distinguishing overlapped classes. This aspect of natural languages considerably affects the building of linguistically interpretable architectures for fuzzy neural networks (FNNs). Here, we propose extending the idea of hedge-embedded linguistic fuzzy neural networks (LiFNNs) to the systems identification and control paradigm. This perspective leads us to the universal approximation property for this mathematical construct using the Stone–Weierstrass theorem and the proof of stability for the resulting nonlinear system identification process using the Lyapunov function. Furthermore, the power activation functions in the membership degrees of the proposed network enable linguistic hedge interpretation and more precise learning. Finally, the proposed LiFNN, optimized using a backpropagation learning algorithm, is evaluated on several problems in function approximation (periodic functions and quadratic Hermite function), system identification (a nonlinear system), and direct adaptive control fields. Results show that memberships are more distinguishable in the proposed LiFNN, leading to ∼50% less error on the average and higher granulation and interpretability. © 2020 IEEE.

关键词： Linguistics

来源：评论

学校读者我要写书评

暂无评论

PHCG: Optimizing Simulink Code Generation for embedded System With SIMD Instructions

引用

IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2023年第4期42卷 1072-1084页

作者： Su, Zhuo Wang, Dongyan Yu, Zehong Yang, Yixiao Jiang, Yu Wang, Rui Chang, Wanli Li, Wen Cui, Aiguo Sun, Jiaguang Tsinghua Univ Sch Software KLISS BNRist Beijing 100084 Peoples R China Renmin Univ China Informat Technol Ctr Beijing 100872 Peoples R China Capital Normal Univ Informat Engn Coll Beijing 100048 Peoples R China Hunan Univ Coll Comp Sci & Elect Engn Changsha 410082 Peoples R China Huawei Technol Co Ltd Godel Labs Shanghai 200120 Peoples R China

Simulink is widely used for the model-driven design of embedded systems. It is able to generate optimized embedded control software code through expression folding, variable reuse, etc. However, for some commonly used computing-sensitive models, such as the models for signal processing applications, the efficiency of the generated code is still limited. In this article, we propose PHCG, an optimized code generator for the Simulink model with single-instruction-multiple-data (SIMD) instruction synthesis. It will select the optimal implementations for intensive computing actors based on adaptively precalculation of the input scales, and synthesize the appropriate SIMD instructions for batch computing actors based on the iterative dataflow graph mapping. In addition, actors of the same type that can be executed in parallel can be combined into batch computing actors as much as possible by merging isomorphic subgraphs. We implemented and evaluated its performance on benchmark Simulink models. Compared to the built-in Simulink Coder and the most recent DFSynth, the code generated by PHCG achieves an improvement of 38.9%-92.9% and 41.2%-76.8% in terms of execution time across different architectures and compilers, respectively.

关键词： Codes Computational modeling Software packages Data models Merging Integrated circuit modeling Computer architecture Code generation model-driven design Simulink single-instruction--multiple-data (SIMD) instruction

来源：评论

学校读者我要写书评

暂无评论

Requirements for Adaptive Consumer Gateways in Residential Learning Healthcare systems: Bringing Intelligence to the Edge

引用

IEEE transactions ON CONSUMER ELECTRONICS 2024年第1期70卷 4457-4469页

作者： Fares, Nada Sherratt, R. Simon Univ Reading Dept Biomed Engn Reading RG6 6AY England

A gateway is a key component in residential healthcare systems. Enabling adaptability and applying intelligence to the gateway will promote residential healthcare systems to become Learning Healthcare systems (LHSs) that can perform real-time decision making. This leads to the exciting potential of a new research field inconsumer-oriented gateways and consumer products that can adapt to the consumer's healthcare needs, learn about the consumer, and over time can adapt accordingly. While consumer healthcare gateways exist, they have tended to be fixed on specific medical conditions and are not upgradeable or adaptive. To be able to create adaptive consumer gateways for consumer healthcare applications, this paper identifies a set of requirements concerning scalability, energy efficiency, reliability, availability, interoperability, and privacy that need to be fulfilled before any product or service can be created. Intervention in local data processing, local data storage, embedded data mining, security, interoperability, and configurability that serve the development process are also discussed. The goal of this paper isto provide the requirements for the innovation of a one-for-all smart adaptive consumer gateway in residential learning healthcare systems and to influence the consumer healthcare field to consider the benefits of moving to adaptive gateways for future developments.

关键词： Adaptive gateways residential healthcare systems learning healthcare systems edge computing machine learning

来源：评论

学校读者我要写书评

暂无评论

Tri-HD: Energy-Efficient On-Chip Learning With In-Memory Hyperdimensional computing

引用

IEEE transactions ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2025年第2期44卷 525-539页

作者： Xu, Weihong Gupta, Saransh Morris, Justin Shen, Xincheng Imani, Mohsen Aksanli, Baris Rosing, Tajana Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92093 USA IBM Res Almaden San Jose CA 95120 USA Calif State Univ Dept Comp Engn San Marcos CA 92096 USA Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA San Diego State Univ Dept Elect & Comp Engn San Diego CA 92182 USA

The Internet of Things (IoT) has led to the emergence of big data. Processing this data, specially in learning algorithms, poses a challenge for current embedded computing systems. Brain-inspired hyperdimensional (HD) computing reduces several complex learning operations to simpler bitwise and arithmetic operations. However, it requires the use of large dimensional vectors, hypervectors, further increasing the amount of data to be processed. Processing in-memory (PIM) enables in-place computation which reduces data movement, a major latency bottleneck in conventional systems. In this article, we propose Tri-HD, an in-memory HD computing architecture that performs HD classification in memory. To the best of authors' knowledge, Tri-HD is the first ReRAM PIM architecture to implement the complete HD computing-based classification pipeline, including encoding, training, retraining, and inference for nonbinary data. We also propose a novel distance metric that is PIM-friendly and provides similar application accuracy as the more complex baseline metric. Our proposed architecture is enabled in PIM by fast and energy-efficient in-memory logic operations. We exploit the voltage threshold-based memristors to enable single cycle operations. We also increase the amount of in-memory parallelism in our design by segmenting bitlines using switches. Our evaluation shows that for all applications tested using HD, Tri-HD provides on average 434x(2170x) speedup and consumes 4114x(26019x) less energy as compared to the CPU while running end-to-end HD training (inference). Tri-HD also achieves at least 2.2% higher-classification accuracy than the existing PIM-based HD designs.

关键词： Training Logic Vectors Memristors Accuracy Indexes Encoding Classification hyperdimensional (HD) computing machine learning memristors nonvolatile memories processing in-memory (PIM) RRAM

来源：评论

学校读者我要写书评

暂无评论

Fraud Feature Boosting Mechanism and Spiral Oversampling Balancing Technique for Credit Card Fraud Detection

引用

IEEE transactions ON COMPUTATIONAL SOCIAL systems 2024年第2期11卷 1615-1630页

作者： Ni, Lina Li, Jufeng Xu, Huixin Wang, Xiangbo Zhang, Jinquan Shandong Univ Sci & Technol Coll Comp Sci & Engn Qingdao 266590 Peoples R China Tongji Univ Key Lab Minist Educ Embedded Syst & Serv Comp Shanghai 201804 Peoples R China Shandong Univ Sci & Technol Coll Comp Sci & Engn Qingdao 266590 Peoples R China

With the flourishing of the credit card business and Internet technology, the risk of fraudulent credit card transactions is ever-increasing due to the complex information involved in the credit card business. Since the high redundancy of feature information and imbalance of class distribution in transaction data, the performance of the existing machine learning-based models for detecting credit card fraudulent transactions still needs to be improved. Therefore, it is crucial to build fraud detection models for effective feature engineering and sampling techniques. This article proposes a credit card fraud detection model incorporating a fraud feature-boosting mechanism with a spiral oversampling balancing technique (SOBT). Specifically, we present a compound grouping elimination strategy to exclude highly redundant and correlated features from the credit card transaction dataset and improve the data quality. Furthermore, we design a multifactor synchronous embedding mechanism, which combines the performance evaluation metrics of the embedding model for each feature and improves the decision-making ability of each feature for the target domain. Moreover, we propose an SOBT to balance the ratio of legitimate to fraudulent transactions, which improves the ability of the fraud detection model to distinguish legitimate from fraudulent transactions. Extensive experimental results based on two real-world datasets demonstrate that our methods can facilitate efficient credit card fraud detection and achieve better performance than state-of-the-art methods.

关键词： Fraud Feature extraction Credit cards Data models Task analysis Redundancy Predictive models Credit card fraud detection feature boosting multifactor embedding oversampling technique

来源：评论

学校读者我要写书评

暂无评论

Power-Efficient and Aging-Aware Primary/Backup Technique for Heterogeneous embedded systems

IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING

引用

IEEE transactions ON SUSTAINABLE computing 2023年第4期8卷 715-726页

作者： Ansari, Mohsen Safari, Sepideh Rohbani, Nezam Ejlali, Alireza Al-Hashimi, Bashir M. Sharif Univ Technol Dept Comp Sci & Engn Tehran *** Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran 193955531 Iran Kings Coll London Dept Engn London WC2R 2LS England

One of the essential requirements of embedded systems is a guaranteed level of reliability. In this regard, fault-tolerance techniques are broadly applied to these systems to enhance reliability. However, fault-tolerance techniques may increase power consumption due to their inherent redundancy. For this purpose, power management techniques are applied, along with fault-tolerance techniques, which generally prolong the system lifespan by decreasing the temperature and leading to an aging rate reduction. Yet, some power management techniques, such as Dynamic voltage and frequency scaling (DVFS), increase the transient fault rate and timing error. For this reason, heterogeneous multicore platforms have received much attention due to their ability to make a trade-off between power consumption and performance. Still, it is more complicated to map and schedule tasks in a heterogeneous multicore system. In this paper, for the first time, we propose a power management method for a heterogeneous multicore system that reduces power consumption and tolerates both transient and permanent faults through primary/backup technique while considering core-level power constraint, real-time constraint, and aging effect. Experimental evaluations demonstrate the efficiency of our proposed method in terms of reducing power consumption compared to the state-of-the-art schemes, together with guaranteeing reliability and considering the aging effect.

关键词： Reliability Aging Task analysis Power demand Multicore processing Fault tolerant systems Fault tolerance Primary/backup power management aging task scheduling heterogeneous embedded systems

来源：评论

学校读者我要写书评

暂无评论

Application Specific Approximate Behavioral Processor

IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING

引用

IEEE transactions ON SUSTAINABLE computing 2023年第2期8卷 165-179页

作者： Si, Qilin Chowdhury, Prattay Sreekumar, Rohit Schafer, Benjamin Carrion Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

Many applications require simple controllers that continuously run the same application. These applications are often found in battery operated embedded systems that require to be ultra-low power (ULP) and are very price sensitive. Some examples include IoT devices of different nature and medical devices. Currently, these systems rely on off-the-shelf general-purpose microprocessors. One of the problems of using these processors, is that not all of the resources are needed for a specific application. Furthermore, because of the regularity of the workloads running on these systems there is a large opportunity to optimize the processor by pruning those unused resources to achieve lower area (cost) and power. Moreover, these processors can be specified at the behavioral level and use High-Level Synthesis (HLS) to generate an efficient Register Transfer Level (RTL) description. This opens a window to additional optimizations as the processor implementation is fully re-optimized during the HLS process. Also, many applications running on these embedded systems tolerate imprecise outputs. These include image processing and digital signal processing (DSP) applications. This opens the door to further optimizations in the context of approximate computing. To address these issues, this work presents a methodology to customize a behavioral RISC processor automatically for a given workload such that its area and power are significantly reduced as compared to the original, general-purpose processor. First, generating a bespoke processor that leads to the exact output as compared to the original general-purpose one and then by approximating it allowing a certain level of error at the output. Compared to previous work that customizes a given processor at the gate netlist only, our proposed method shows significant benefits. In particular, this work shows that raising the level of abstraction reduces the area and power by 78.3% and 70.1% for the exact solution on average, and furthe

关键词： Logic gates Behavioral sciences Optimization Process control Registers Hardware Very large scale integration Approximate computing bespoke behavioral processors high-level synthesis

来源：评论

学校读者我要写书评

暂无评论

Harnessing Machine Learning in Dynamic Thermal Management in embedded CPU-GPU Platforms

引用

ACM transactions ON DESIGN AUTOMATION OF ELECTRONIC systems 2025年第2期30卷 1-32页

作者： Maity, Srijeeta Majumder, Anirban Roy, Rudrajyoti Hota, Ashish Dey, Soumyajit Indian Inst Technol Kharagpur Comp Sci & Engn Kharagpur West Bengal India Indian Inst Technol Kharagpur Elect Engn Kharagpur West Bengal India Indian Inst Technol Kharagpur Electron & Commun Engn Kharagpur West Bengal India

With increasing transistor density, modern heterogeneous embedded processors often exhibit high temperature gradients due to complex application scheduling scenarios which may have missed design considerations. In many use cases, off-chip "active" cooling solutions are considered prohibitive in such reduced form factors. Core frequency throttling by existing dynamic thermal management techniques often compromises the Quality-of-Service (QoS) and violates real-time deadlines. This necessitates the adoption of intelligent resource management that simultaneously manages both thermal and latency performance. Coupled with the complexity of modern heterogeneous multi-cores, the periodic application updates that cater to everchanging user requirements often render model-driven thermal-aware resource allocation approaches unsuitable for heterogeneous multi-core systems. For such application-architecture scenarios, we propose a novel self-learning based resource manager using Reinforcement Learning that intelligently manipulates core frequencies and task set mappings to fulfill thermal and latency objectives. Our framework employs a datadriven system modeling technique using Gaussian Process Regression to enable efficient offline training of this learning-based resource manager to avoid challenges associated with initial online training. We evaluate the approach on a heterogeneous embedded CPU-GPU platform with real workloads and observe a significant reduction in peak operating temperature when compared to the default onboard frequency governor as well as other learning-based state-of-the-art approaches.

关键词： Computer systems organization-Real-time systems Parallel architectures Hardware-Thermal issues Q-Learning adaptive thermal management heterogeneous computing gaussian process regression reinforcement learning

来源：评论

学校读者我要写书评

暂无评论

An in-Array Build-In Self-Test Scheme for embedded SRAM Array

引用

IEEE transactions ON CIRCUITS AND systems II-EXPRESS BRIEFS 2024年第8期71卷 3935-3939页

作者： Wei, Feng Cui, Xiaole Zhang, Sunrui Peking Univ Shenzhen Grad Sch Key Lab Integrated Microsyst Shenzhen 518055 Peoples R China Peng Cheng Lab Dept Networked Intelligence Shenzhen 518055 Peoples R China

An in-array Build-In Self-Test (BIST) scheme is proposed for the embedded SRAM array. The linear feedback shift register (LFSR) is used to implement the pattern generator, and the single/multiple-input signature register (SISR/MISR) is used to implement the response compactor. The proposed BIST scheme only consumes half the number of transistors and area compared with the conventional LFSR/MISR BIST, and it is testable. The conventional BIST circuit outside the SRAM array is unnecessary if the proposed BIST scheme is applied. The proposed BIST scheme is able to implement various March sequences to test the other part of the memory array.

关键词： Built-in self-test Generators SRAM cells Logic gates Transistors Discharges (electric) Voltage SRAM test LFSR SISR/MISR in-array build-in-self-test in-memory computing

来源：评论

学校读者我要写书评

暂无评论

The Real-Time Pavement Distress Detection System Based on Edge-Cloud Collaborative computing

引用

IEEE transactions ON INTELLIGENT TRANSPORTATION systems 2025年

作者： Liu, Yuchen Liu, Fang Huang, Yucheng Hu, Jing Zhang, Wei Hou, Yue Soochow Univ Sch Rail Transportat Suzhou 215131 Peoples R China Xian Jiaotong Liverpool Univ Acad Creat Technol Suzhou 215123 Peoples R China Southeast Univ Intelligent Transportat Syst Res Ctr Nanjing 211189 Peoples R China Chewy Inc Boston MA 02210 USA Swansea Univ Dept Civil Engn Swansea SA1 8EN Wales

Most advanced methods for road surface defect detection may have the issue of large network structures, making them impractical for implementation on mobile embedded systems. In this study, A lightweight road surface defect real-time intelligent detection system based on cloud-edge collaboration is proposed. The system comprises a lightweight feature-enhanced YOLO network (YOLO-LFE), a multi-object tracking network called ByteTrack, and is deployed on intelligent edge devices, enabling real-time defect detection and storage of uploaded defect information through edge computing modules and cloud systems. Built upon the latest YOLOv8 architecture, a lightweight MobileNetV3 network is first introduced as the backbone feature extraction component, resulting in a noteworthy decrease in parameters and computational intricacy. Subsequently, the Enhanced Spatial Pyramid Pooling (ESPP) method built upon the human visual perception system is applied to swap out the Spatial Pyramid Pooling Fusion (SPPF) method, thereby enhancing the model's capability to capture features from tiny entities. Finally, an enhanced progressive feature fusion network is designed to further address the semantic gap issue during subsequent fusion of primary features. Experimental results on a self-made dataset and the public RDD2022 dataset show that the proposed detection model maintains high accuracy while requiring fewer parameters and less computational resources. Compared to YOLOv8, the model reduces the number of parameters by 32.5% and decreases computational requirements by 37%. This makes it more suitable for deployment on embedded devices. Additionally, the system has been field-tested on vehicles, thereby validating the effectiveness of the entire system.

关键词： Computational modeling Roads Real-time systems Accuracy Feature extraction Defect detection YOLO Image edge detection Convolution Servers Pavement distress efficient receptive field block enhanced asymptotic feature pyramid network ByteTrack

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：