The proceedings contain 17 papers. The topics discussed include: quick and practical run-time evaluation of multiple program optimizations;specializing cache structures for highperformance and energy conservation in ...
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ISBN:
(纸本)3540715274
The proceedings contain 17 papers. The topics discussed include: quick and practical run-time evaluation of multiple program optimizations;specializing cache structures for highperformance and energy conservation in embedded systems;power aware external bus arbitration for system-on-a-chip embedded systems;convergent compilation applied to loop unrolling;finding and applying loop transformations for generating optimized FPGA implementations;dynamic and on-line design space exploration for reconfigurable architectures;automatic discovery of coarse-grained parallelism in media applications;static cache partitioning robustness analysis for embedded on-chip multi-processors;selective code compression scheme for embedded systems;and a prefetching algorithm for multi-speed disks.
The proceedings contain 15 papers. The topics discussed include: recruiting decay dynamic power reduction in self-associative caches;compiler-assisted memory encryption for embedded processors;branch predictor warmup ...
ISBN:
(纸本)3642009034
The proceedings contain 15 papers. The topics discussed include: recruiting decay dynamic power reduction in self-associative caches;compiler-assisted memory encryption for embedded processors;branch predictor warmup for sampled simulation through branch history matching;data cache techniques to save power and deliver highperformancein embedded systems;combining edge vector and event counter for time-dependent power behavior characterization;accurate instruction pre-scheduling in dynamically scheduled processors;fetch gating control through speculative instruction window weighting;fast code generation for embedded processors with aliased heterogeneous registers;a context-parameterized model for static analysis of execution times;reexecution and selective reuse in checkpoint processors;and compiler support for code size reduction using a queue-based processor.
The rapid growth of demanding applications in domains applying multimedia processing and machine learning has marked a new era for edge and cloud computing. These applications involve massive data and compute-intensiv...
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The rapid growth of demanding applications in domains applying multimedia processing and machine learning has marked a new era for edge and cloud computing. These applications involve massive data and compute-intensive tasks, and thus, typical computing paradigms in embedded systems and data centers are stressed to meet the worldwide demand for highperformance. Concurrently, over the last 15 years, the semiconductor industry has established power efficiency as a first-class design concern. As a result, the community of computing systems is forced to find alternative design approaches to facilitate high-performance and power-efficient computing. Among the examined solutions, Approximate Computing has attracted an ever-increasing interest, which has resulted in novel approximation techniques for all the layers of the traditional computing stack. More specifically, during the last decade, a plethora of approximation techniques in software (programs, frameworks, compilers, runtimes, languages), hardware (circuits, accelerators), and architectures (processors, memories) have been proposed in the literature. The current article is Part i of a comprehensive survey on Approximate Computing. it reviews its motivation, terminology, and principles, as well as it classifies the state-of-the-art software & hardware approximation techniques, presents their technical details, and reports a comparative quantitative analysis.
Commercial embedded systems increasingly rely on heterogeneous architectures that integrate general-purpose, multi-core processors, and various hardware accelerators on the same chip. This provides the high performanc...
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Commercial embedded systems increasingly rely on heterogeneous architectures that integrate general-purpose, multi-core processors, and various hardware accelerators on the same chip. This provides the highperformance required by modern applications at a low cost and low power consumption, but at the same time poses new challenges. Hardware resource sharing at various levels, and in particular at the main memory controller level, results in slower execution time for the application tasks, ultimately making the system unpredictable from the point of view of timing. To enable the adoption of heterogeneous systems-on-chip (System on Chips (SoCs)) in the domain of timing-critical applications several hardware and software approaches have been proposed, bandwidth regulation based on monitoring and throttling being one of the most widely adopted. Existing solutions, however, are either too coarse-grained, limiting the control over computing engines activities, or strongly platform-dependent, addressing the problem only for specific SoCs. This article proposes an innovative approach that can accurately control main memory bandwidth usage in FPGA-based heterogeneous SoCs. in particular, it controls system bandwidth by connecting a runtime bandwidth regulation component to FPGA-based accelerators. Our solution offers dynamically configurable, fine-grained bandwidth regulation - to adapt to the varying requirements of the application over time - at a very low overhead. Furthermore, it is entirely platform-independent, capable of integration with any FPGA-based accelerator. Developed at the register-transfer level using a reference SoC platform, it is designed for easy compatibility with any FPGA-based SoC. Experimental results conducted on the Xilinx Zynq UltraScale+ platform demonstrate that our approach (i) is more than 100x faster than loosely-coupled, software controlled regulators;(ii) is capable of exploiting the system bandwidth 28.7% more efficiently than tightly-cou
transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performanceembedded computer systems. Recognizing the convergence&...
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ISBN:
(数字)9783662588345
ISBN:
(纸本)9783662588338
transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performanceembedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.;This 5th issue contains extended versions of papers by the best paper award candidates of iC-SAMOS 2009 and the SAMOS 2009 Workshop, colocated events of the 9th international Symposium on Systems, architectures, Modeling and Simulation, SAMOS 2009, held in Samos, Greece, in 2009. The 7 papers included in this volume were carefully reviewed and selected. The papers cover research on embedded processor hardware/software design and integration and present challenging research trends.
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