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检索条件"任意字段=Working Conference on Massively Parallel Programming Models"

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LIMITATIONS TO parallel PROCESSING

LIMITATIONS TO PARALLEL PROCESSING

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9TH ANNUAL INTERNATIONAL PHOENIX CONF ON COMPUTERS AND COMMUNICATIONS

作者： BURKHARDT, WH Inst fuer Inf Univ Stuttgart West Germany

ISBN: (纸本)0818620307

The reasons why massively parallel processor systems show such dismal performance are analyzed. The degradation by seriality and communication has been investigated theoretically for linear, rectangular, and square configurations and by experiment on a Transputer system of modifiable dimension from 1 to 4, and up to 16 processors. Eight different application programs run can be grouped into academic and practical problems. They are written in a functional programming language for maximal parallelism. The measured results are analyzed by regression. The quadratic polynomial from the theoretical section shows the best fit. Optimal number of processors, maximal systems performance, and communications factors range from 5 to 14, from 2 to 7, and from 1% to 18%, respectively. Analysis of two experiments from literature on a tightly and a loosely coupled system show similar severe performance degradation, depending on configuration and problem type, with excellent applicability of the theoretical models.

关键词： Computer systems, Digital

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Continuous Automatic Speech Recognition System Using MapReduce Framework 7

Continuous Automatic Speech Recognition System Using MapRedu...

引用

7th IEEE International Advanced Computing conference, IACC 2017

作者： Vikram, M. Sudhakar Reddy, N. Madhavi, K. SV College of Engineering India JNTUA College of Engineering India

ISBN: (纸本)9781509015603

Now-A-days, Speech Recognition had become a prominent and challenging research domain because of its vast usage. The factors affecting Speech Recognition are Vocalization, Pitch, Tone, Noise, Pronunciation, Frequency, finding where the phoneme starts and stops, Loudness, Speed, Accent and so on. Research is going on to enhance the efficacy of Speech Recognition. Speech Recognition requires efficient models, algorithms and programming frameworks to analyze large amount of real-Time data. These algorithms and programming paradigms have to learn knowledge on their own to fit in to the model for massively evolving data in real-Time. The developments in parallel computing platforms opens four major possibilities for Speech Recognition systems: improving recognition accuracy, increasing recognition throughput, reducing recognition latency and reducing the recognition training period. © 2017 IEEE.

关键词： Hidden Markov models

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GPU Delegation: Toward a Generic Approach for Developping MABS using GPU programming 15

GPU Delegation: Toward a Generic Approach for Developping MA...

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15th International conference on Autonomous Agents and Multiagent Systems (AAMAS)

作者： Hermellin, Emmanuel Michel, Fabien Univ Montpellier CNRS LIRMM 161 Rue Ada F-34095 Montpellier France

ISBN: (纸本)9781450342391

Using Multi-Agent Based Simulation (MABS), computing resources requirements often limit the extent to which a model could be experimented. As the number of agents and the size of the environment are constantly growing in these simulations, using General-Purpose Computing on Graphics Units (GPGPU) appears to be very promising as it allows to use the massively parallel architecture of the GPU (Graphics Processing Unit) to do High Performance Computing (HPC). Considering the use of GPGPU for developing MABS, the conclusions of Perumalla and Aaby's work [25] in 2008 was twofold: (1) data parallel execution capabilities of GPU can be used effectively in MABS and afford excellent speedup on models and (2) effective use of data parallel execution requires resolution of modeling and execution challenges at the cost of a decrease in modularity, ease of programmability and reusability. In this paper, we propose to study through experiments if the conclusions and issues outlined by Perumalla and Aaby are still true despite the evolution of GPGPU and MABS. To this end, we use the GPU environmental delegation principle on four models in order to compare CPU and GPU implementations. Then, we discuss and analyze the results from both a conceptual and a performance point of view.

关键词： MABS GPGPU CUDA Hybrid architecture

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Limits on speculative module-level parallelism in imperative and object-oriented programs on CMP platforms

Limits on speculative module-level parallelism in imperative...

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International conference on parallel Architectures and Compilation Techniques

作者： Warg, F Stenström, P Chalmers Univ Technol Dept Comp Engn SE-41296 Gothenburg Sweden

ISBN: (纸本)0769513638

This paper considers program modules, e.g. procedures, functions, and methods cis the basic method to exploit speculative parallelism in existing codes. We analyze how much inherent and exploitable parallelism exist in a set of C and Java programs on a set of chip-multiprocessor architecture models, and identify what inherent program features, as well as architectural deficiencies, that limit the speedup. Our data complement previous limit studies by indicating that the programming style - object-oriented versus imperative - does not seem to have any noticeable impact on the achievable speedup. Further we show that as few as eight processors are enough to exploit all of the inherent parallelism. However, memory-level data dependence resolution and thread management mechanisms of recent CMP proposals may impose overheads that severely limit the speedup obtained.

关键词： Object oriented programming

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massively parallel Feature Extraction Framework Application in Predicting Dangerous Seismic Events

Massively Parallel Feature Extraction Framework Application ...

引用

Federated conference on Computer Science and Information Systems (FedCSIS)

作者： Cirzegorowski, Marek Univ Warsaw Fac Math Informat & Mech Banacha 2 PL-02097 Warsaw Poland

ISBN: (纸本)9788360810903

In this paper we introduce an automated mechanism for knowledge discovery from data streams. As a part of this work, we also present a new approach to the creation of classifiers ensemble based on a wide variety of models. Furthermore, we describe an innovative, highly scalable feature extraction and selection framework designed to work with the MapReduce programming model and the application of designed framework to build an ensemble of classifiers which takes into account both the quality and the diversity of individual models. The effectiveness of the solution has been verified through a participation in an open data mining competition which concerned the problem of predicting periods of increased seismic activity causing life threatening accidents in coal mines. The submitted solution obtained the highest AUC score of all the solutions uploaded by 106 participating research teams.

关键词： Data mining

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Efficient steepest-edge simplex algorithm for SIMD computers

Efficient steepest-edge simplex algorithm for SIMD computers

引用

Proceedings of the 1996 International conference on Supercomputing

作者： Thomadakis, Michael E. Liu, Jyh-Charn Texas A&M Univ College Station TX United States

This paper proposes a new implementation of the Primal and Dual Simplex algorithms for Linear programming problems on massively parallel SIMD computers. The algorithms are based on the Steepest-Edge pivot selection method and the tableau representation of the constraint matrix. The parallel algorithm reduces communication overhead by maintaining local replicas of key portions of the tableau along with the sub-matrices on each one of the PEs. The Steepest-Edge method utilizes mainly local information to search for the next pivot element. Pivot rows and columns are efficiently broadcasted to PEs before pivot steps, utilizing the geometry of pipelined, toroidal mesh interconnection network. The proposed parallelization has optimal asymptotic speedup and scalability properties and experimental results show that as problem sizes increase the speedups obtained by MasPar's MP-1 and MP-2 models are in the order of 100 times, and 1000 times, respectively, over sequential Steepest-Edge Simplex running on high-end Unix workstations.

关键词： parallel algorithms

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Datarol: a parallel machine architecture for fine-grain multithreading

Datarol: a parallel machine architecture for fine-grain mult...

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working conference on massively parallel programming models

作者： M. Amamiya H. Tomiyasu S. Kusakabe Department of Intelligent Systems Kyushu University Fukuoka Japan

We discuss a design principle of massively parallel distributed-memory multiprocessor architecture which solves latency problem, and present the Datarol machine architecture. Latencies, caused by remote memory access and remote procedure call, are most serious problems in massively parallel computers. In order to eliminate the processor idle times caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes. First, we present a processor architecture, called Datarol-II, that promotes efficient fine-grain multithread execution by performing fast context switching among fine-grain concurrent processes. In the Datarol-II processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memory access overhead caused by context switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. Then, we present a cost-effective design of the Datarol-II processor, which incorporates off-the-shelf high-end microprocessor while preserving the fine-grain dataflow concept. The off-the-shelf microprocessor Pentium is used for its core processing, and a co-processor called FMP (Fine-grain Message Processor) is designed for fine grained message handling and communication controls. The co-processor FMP is designed on the basis of FMD (Fine-grain Message Driven) execution model, in which fine-grain multi-threaded execution is driven and controlled by simple fine-grain message communications.

关键词： parallel machines Computer architecture Delay Microprocessors Coprocessors Communication system control Concurrent computing Registers Pipelines Load flow control

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programming for GPUs: the Directive-Based Approach

Programming for GPUs: the Directive-Based Approach

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8th International conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Grillo, Lucas de Sande, Francisco Fumero, Juan J. Reyes, Ruyman Univ La Laguna Dept EIO & Comp San Cristobal la Laguna 38271 Spain Inst Tecnol Energias Renowables Granada Spain Univ Edinburgh Edinburgh Parallel Comp Ctr Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9780769550947

In the last years, hardware accelerators, such as GPUs have become ubiquitous in the HPC landscape and GPGPU has been massively adopted by the HPC research community. If something is slowing down further expansion of this technology are its difficulties in terms of programmability. Although several libraries and applications providing GPU support are available, the need of implementing new algorithms from scratch, or adapting sequential programs to accelerators, still exist. Writing programs to be executed on accelerators is not easy, particularly for non-expert developers coming from the science or engineering fields, as it requires deep understanding of the underlying architecture. Different alternatives have appeared aimed to diminish the GPU programming effort. In the wake of the success of OpenMP, several directive-oriented programming models have been created. Although future OpenMP releases will integrate accelerators, tools are needed in the meantime. In this work, we present a comparison of directive-based approaches for GPU platforms, hiCUDA, PGI Accelerator and OpenACC. For the last, in addition to the two commercial compilers available, we include results using accULL, our own OpenACC implementation. To illustrate the portability of these alternatives, we show performance figures for both Fermi and Kepler NVIDIA cards.

关键词： CUDA Compilers GPGPU HMPP OpenACC PGI accULL

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Scalable multicomputer object spaces: a foundation for high performance systems

Scalable multicomputer object spaces: a foundation for high ...

引用

working conference on massively parallel programming models

作者： S.M. Blackburn R.B. Stanton Dept. of Comput. Sci. Australian Nat. Univ. Canberra ACT Australia Department of Computer Science Australian National University Canberra ACT Australia

The development of scalable architectures at store levels of a layered model has concentrated on processor parallelism balanced against scalable memory bandwidth, primarily through distributed memory structures of one kind or another. A great deal of attention has been paid to hiding the distribution of memory to produce a single store image across the memory structure. It is unlikely that the distribution and concurrency aspects of scalable computing can be completely hidden at that level. This paper argues for a store layer which respects the need for caching and replication, and to do so at an "object" level granularity of memory use. These facets are interrelated through atomic processes, leading to an interface for the store which is strongly transactional in character. The paper describes the experimental performance of such a layer on a scalable multi-computer architecture. The behaviour of the store supports the view that a scalable cached "transactional" store architecture is a practical objective for high performance based on parallel computation across distributed memories.

关键词： High performance computing Computer architecture Concurrent computing Distributed computing Bandwidth parallel processing Scalability Computer science Atomic layer deposition Large-scale systems

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1st International ACPC conference on parallel Computation, 1991

1st International ACPC Conference on Parallel Computation, 1...

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1st International ACPC conference on parallel Computation, 1991

ISBN: (纸本)9783540554370

The proceedings contain 33 papers. The special focus in this conference is on parallel Computation. The topics include: Scalable cache coherence for shared memory multiprocessors;new program restructuring technology;data parallel program design;a powerful high-level debugger for parallel programs;the PCP/PFP programming models on the BBN TC2000;knowledge-based parallelization for distributed memory systems;parallelization for multiprocessors with memory hierarchies;data structures for optimizing programs with explicit parallelism;MODULA-S: a language to exploit two dimensional parallelism;ADAPTing fortran 90 array programs for distributed memory architectures;evolution of massive parallel compute servers from a research object to a production pool;processor scheduling in multiprocessor systems;multipacket routing on rings;massively parallel processing in high energy physics: the CERN-MPPC project;a heuristic algorithm for dynamic task allocation in highly parallel systems;analysis of parallel lisp programs based on a trace mechanism;a distributed implementation of flat concurrent prolog on multi-transputer environments;negation in conclog;symbolic computation and parallel software;on the parallelization of characteristic-set-based algorithms;multiplication as parallel as possible;on the existence of an efficient parallel algorithm for a graph theoretic problem;on the multi-threaded computation of modular polynomial greatest common divisors;a buchberger algorithm for distributed memory multiprocessors;computational biology on massively parallel machines;time-parallel multigrid in an extrapolation method for time-dependent partial differential equations;parallelization of simulation tasks: methodology - implementation -application;parallel algorithms for stress analysis on shared-memory multiprocessors and elastic load-balancing for image processing algorithms.

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