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KRIPKE-A massively parallel transport mini-app

KRIPKE-A massively parallel transport mini-app

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Mathematics and Computations, Supercomputing in Nuclear Applications and Monte Carlo International conference, M and C+SNA+MC 2015

作者： Kunen, Adam J. Bailey, Teresa S. Brown, Peter N. Lawrence Livermore National Laboratory LivermoreCA94551 United States

ISBN: (纸本)9781510808041

As computer architectures become more complex, developing high performance computing codes becomes more challenging. Processors are getting more cores, which tend to be simpler and support multiple hardware threads, and ever wider SIMD (vector) units. Memory is becoming more hierarchical with more diverse bandwidths and latencies. GPU's push these trends to an extreme. Existing simulation codes that had good performance on the previous generation of computers will most likely not perform as well on new architectures. Rewriting existing codes from scratch is a monumental task. Refactoring existing codes is often more tractable. Proxy Applications are proving to be valuable research tools that help explore the best approaches to use in existing codes. They provide a much smaller code that can be refactored or rewritten at little cost, but provide insight into how the parent code would behave with a similar (but much more expensive) refactoring effort. In this paper we introduce KRIPKE, a mini-app developed at Lawrence Livermore National Laboratory, designed to be a proxy for a fully functional discrete-ordinates (SN) transport code. KRIPKE was developed to study the performance characteristics of data layouts, programming models, and sweep algorithms. KRIPKE is designed to support different in-memory data layouts, and allows work to be grouped into sets in order to expose more on-node parallelism. Different data layouts change the way in which software is implemented, how that software is compiled for a given architecture, and how that generated code eventually performs on a given architecture.

关键词： Memory architecture

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Continuous engineering of embedded systems 1

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5th IFIP TC 10 working conference on Distributed and parallel Embedded Systems, DIPES 2006

作者： Steffen, Bernhard Margaria, Tiziana Chair of Programming Systems Universität Dortmund Germany Chair of Service and Software Engineering Universität Potsdam Germany

ISBN: (数字)9780387393629

ISBN: (纸本)9780387393612

We investigate the late phases of the embedded systems’ life cycles, in particular the treatment of change requests, the integration of legacy components, and the problem of emerging platforms. We propose to tackle these issues in a model-driven design paradigm, on the behavioral models, and to employ techniques from automata theory, model checking and automata learning. The main practical impact of our approach is its support of the systematic completion and update of user/customer requirements, which by their nature are quite partial and concentrate on the most prominent scenarios. Our technique generalizes these typical requirement skeletons by extrapolation and it indicates via automatically generated traces where the requirement specification is too loose and additional information is required. This works in the initial phases of system development, but also in case of change requests, where our technique hints at possible problems with their realization (feature interactions), and helps to keep the requirement model in synchrony along the chain of new releases. © 2006 by International Federation for Information Processing.

关键词： Embedded systems

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Views on template-based parallel programming 96

Views on template-based parallel programming

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Proceedings of the 1996 conference of the Centre for Advanced Studies on Collaborative research

作者： Ajit Singh Jonathan Schaeffer Duane Szafron University of Waterloo Dept. of Electrical and Computer Eng. Waterloo Ontario Canada N2L 3G1 University of Alberta Dept. of Computing Science Edmonton Alberta Canada T6G 2H1

For almost a decade we have been working at developing and using template-based models for coarse-grained parallel computing. Our initial system, FrameWorks, was positively received but had a number of shortcomings. The Enterprise parallel programming environment evolved out of this work, and now, after several years of experience with the system, its shortcomings are becoming evident. This paper outlines our experiences in developing and using the two parallel programming systems. Many of our observations are relevant to other parallel programming systems, even though they may be based on different assumptions. Although template-base models have the potential for simplifying the complexities of parallel programming, they have yet to realize these expectations for high-performance applications.

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massively parallel Network Coding on GPUs

Massively Parallel Network Coding on GPUs

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IEEE International conference on Performance, Computing and Communications (IPCCC)

作者： Xiaowen Chu Kaiyong Zhao Mea Wang Department of Computer Science Hong Kong Baptist University Hong Kong China Department of Computer Science University of Calgary AB Canada

Network coding has recently been widely applied in various networks for system throughput improvement and/or resilience to network dynamics. However, the computational overhead introduced by the network coding operations is not negligible and has become the cornerstone for real deployment of network coding. In this paper, we exploit the computing power of contemporary Graphic Processing Units (GPUs) to accelerate the network coding operations. We proposed three parallel algorithms that maximize the parallelism of the encoding and decoding processes, i.e., the power of GPUs is fully utilized. This paper also shares our optimization design choices and our workarounds to the challenges encountered in working with GPUs. With our implementation of the algorithms, we are able to achieve up to 12 times of speedup over the highly optimized CPU counterpart, using the NVIDIA GPU and the Computer Unified Device Architecture (CUDA) programming model.

关键词： Network coding Computer networks Throughput Resilience Graphics Acceleration parallel algorithms parallel processing Encoding Decoding

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programming for GPUs: The Directive-Based Approach

Programming for GPUs: The Directive-Based Approach

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International conference on P2P, parallel, Grid, Cloud and Internet Computing (3PGCIC)

作者： Lucas Grillo Francisco De Sande Juan J. Fumero Ruymán Reyes Dept. de EIO y Computación Universidad de La Laguna La Laguna Spain Instituto Tecnológico de Energías Renovables Granadilla de Abona Spain Edinburgh Parallel Computing Centre University of Edinburgh Edinburgh UK

In the last years, hardware accelerators, such as GPUs have become ubiquitous in the HPC landscape and GPGPU has been massively adopted by the HPC research community. If something is slowing down further expansion of this technology are its difficulties in terms of programmability. Although several libraries and applications providing GPU support are available, the need of implementing new algorithms from scratch, or adapting sequential programs to accelerators, still exist. Writing programs to be executed on accelerators is not easy, particularly for non-expert developers coming from the science or engineering fields, as it requires deep understanding of the underlying architecture. Different alternatives have appeared aimed to diminish the GPU programming effort. In the wake of the success of OpenMP, several directive-oriented programming models have been created. Although future OpenMP releases will integrate accelerators, tools are needed in the meantime. In this work, we present a comparison of directive-based approaches for GPU platforms, hiCUDA, PGI Accelerator and OpenACC. For the last, in addition to the two commercial compilers available, we include results using accULL, our own OpenACC implementation. To illustrate the portability of these alternatives, we show performance figures for both Fermi and Kepler NVIDIA cards.

关键词： Graphics processing units Kernel programming Standards Runtime parallel processing

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Limitations to parallel processing

Limitations to parallel processing

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International Phoenix conference on Computers and Communications (IPCCC)

作者： W.H. Burkhardt Institut für Informatik Universität Stuttgart Stuttgart Germany

The reasons why massively parallel processor systems show such dismal performance are analyzed. The degradation by seriality and communication has been investigated theoretically for linear, rectangular, and square configurations and by experiment on a Transputer system of modifiable dimension from 1 to 4, and up to 16 processors. Eight different application programs run can be grouped into academic and practical problems. They are written in a functional programming language for maximal parallelism. The measured results are analyzed by regression. The quadratic polynomial from the theoretical section shows the best fit. Optimal number of processors, maximal systems performance, and communications factors range from 5 to 14, from 2 to 7, and from 1% to 18%, respectively. Analysis of two experiments from literature on a tightly and a loosely coupled system show similar severe performance degradation, depending on configuration and problem type, with excellent applicability of the theoretical models.< >

关键词： parallel processing Concurrent computing Degradation Art Performance analysis Polynomials System performance Multiprocessing systems Microprocessors Mobile computing

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Automated Performance Prediction of Message-Passing parallel Programs

Automated Performance Prediction of Message-Passing Parallel...

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Supercomputing conference

作者： R.J. Block S. Sarukkai P. Mehra Department of Computer Science University of Illinois Urbana IL USA NASA Ames Research Center Moffett Field CA USA

The increasing use of massively parallel supercomputers to solve large-scale scientific problems has generated a need for tools that can predict scalability trends of applications written for these machines. Much work has been done to create simple models that represent important characteristics of parallel programs, such as latency, network contention, and communication volume. But many of these methods still require substantial manual effort to represent an application in the model's format. The MK toolkit described in this paper is the result of an on-going effort to automate the formation of analytic expressions of program execution time, with a minimum of programmer assistance. In this paper we demonstrate the feasibility of our approach, by extending previous work to detect and model communication patterns automatically, with and without overlapped computations. The predictions derived from these models agree, within reasonable limits, with execution times of programs measured on the Intel iPSC/860 and Paragon. Further, we demonstrate the use of MK in selecting optimal computational grain size and studying various scalability metrics.

关键词： Scalability Performance analysis Predictive models Debugging programming profession High performance computing Large-scale systems Complexity theory Pattern analysis Computer science

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Toward Multiperiod AC-Based Contingency Constrained Optimal Power Flow at Large Scale

Toward Multiperiod AC-Based Contingency Constrained Optimal ...

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Power Systems Computation conference (PSCC)

作者： Michel Schanen François Gilbert Cosmin G. Petra Mihai Anitescu Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA Lawrence Livermore National Laboratory Center for Applied Scientific Computing Livermore CA USA

This work presents a scaling study of a parallel nonlinear, nonconvex optimization approach applied to a multiperiod contingency constrained alternating current optimal power flow. We propose a “variable duplication” model for efficient parallelization of the numerical optimization on massively parallel HPC hardware. The model is expressed as a two-stage nonlinear programming problem, where the first stage captures time-dependent constraints and the second stage reflects the system changes in response to contingencies. The parallel interior-point optimization solver for nonlinear programming (PIPS-NLP) enables us to leverage the dual-block angular structure specific to the formulation by applying the Schur complement for efficient parallelization of the linear solves. The Julia modelling package StructJuMP, allows us to compactly and conveniently express the model's algebraic components. StructJuMP uses automatic differentiation to provide the first-and second-order derivatives to PIPS-NLP. Aiming at a strategy for computations at petascale, numerical experiments conducted on Theta, an Intel KNL-based system at the Argonne Leadership Computing Facility are presented.

关键词： Optimization Computational modeling Mathematical model Computer architecture Numerical models Reactive power Linear systems

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Towards models for Many-Cores: The Case for the Reconfigurable Mesh

Towards Models for Many-Cores: The Case for the Reconfigurab...

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22th International conference on Architecture of Computing Systems 2009

作者： Heiner Giefers Marco Platzner University of Paderborn Germany

ISBN: (纸本)9783800731336

The reconfigurable mesh has been extensively studied as a theoretical model for massively parallel computing, but its implementation has been severely hindered by the unrealistic assumption of constant time broadcasts. Nevertheless, we investigate the reconfigurable mesh as a model for future many-cores due to its many interesting features. In this paper, we discuss the realization of such a many-core architecture on FPGA technology and a corresponding tool flow including a new programming language. Then we focus on two important characteristics for a many-core, scalability and fault tolerance. We present reconfigurable mesh algorithms to achieve these characteristics and elaborate on the new challenges faced when applying these algorithms to practical reconfigurable meshes.

关键词： configurability core construction Medical Subject Headings Fault tolerance Mesh algorithms Theoretical models

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VAST: The illusion of a large memory space for GPUs

VAST: The illusion of a large memory space for GPUs

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International conference on parallel Architecture and Compilation Techniques (PACT)

作者： Janghaeng Lee Mehrzad Samadi Scott Mahlke Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA

ISBN: (纸本)9781509066070

Heterogeneous systems equipped with traditional processors (CPUs) and graphics processing units (GPUs) have enabled processing large data sets. With new programming models, such as OpenCL and CUDA, programmers are encouraged to offload data parallel workloads to GPUs as much as possible in order to fully utilize the available resources. Unfortunately, offloading work is strictly limited by the size of the physical memory on a specific GPU. In this paper, we present Virtual Address Space for Throughput processors (VAST), an automatic GPU memory management system that provides an OpenCL program with the illusion of a virtual memory space. Based on the available physical memory on the target GPU, VAST does the following: automatically partitions the data parallel workload into chunks; efficiently extracts the precise working set required for the divided workload; rearranges the working set in contiguous memory space; and, transforms the kernel to operate on the reorganized working set. With VAST, the programmer is responsible for developing a data parallel kernel in OpenCL without concern for physical memory space limitations of individual GPUs. VAST transparently handles code generation dealing with the constraints of the actual physical memory and improves the re-targetability of the OpenCL with moderate overhead. Experiments demonstrate that a real GPU, NVIDIA GTX 760 with 2 GB of memory, can compute any size of data without program changes achieving 2.6× speedup over CPU exeuction, which is a realistic alternative for large data computation.

关键词： Kernel Graphics processing units Memory management Hardware programming

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