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Investigating large-scale feature matching using the Intel® Xeon Phi™ coprocessor

Investigating large-scale feature matching using the Intel®...

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International conference on Image and Vision Computing New Zealand, IVCNZ

作者： Kai-Cheung Leung David Eyers Xiaoxin Tang Steven Mills Zhiyi Huang Department of Computer Science University of Otago New Zealand Department of Computer Science Shanghai Jiao Tong University China

Many computer vision applications are entering the `big data' era: it is straightforward to acquire very large datasets that need to be processed. Our current research targets a large-scale structure-from-motion application, in which 3D models are formed from large collections of digital photographs. There have also been many recent technological developments suitable for speeding up the data processing for these computer vision applications. However many of the emerging technologies have very different costs in terms of developer time and experience. We have previously implemented our system on multicore CPUs, clusters of such multicore machines, and GPUs. The Intel® Xeon Phi™ coprocessor aims to provide highly efficient processing of massively parallel workloads. The Phi tries to strike a pragmatic balance between the vector processing power of GPUs, and the ease of programming provided by deploying to CPUs. Very recently, some Phi coprocessors have been made available through the New Zealand eScience Infrastructure (NeSI) facilities. This paper reports on our initial findings porting and running part of our processing pipeline on the Intel® Xeon Phi™.

关键词： parallel processing Hardware Central Processing Unit Computer architecture Libraries Coprocessors Graphics processing units

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massively parallel programming models used as hardware description languages: The OpenCL case 11

Massively parallel programming models used as hardware descr...

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IEEE International conference on Computer-Aided Design

作者： Muhsen Owaida Nikolaos Bellas Christos D. Antonopoulos Konstantis Daloukas Charalambos Antoniadis Department of Computer and Communication Engineering University of Thessally Volos Greece

ISBN: (纸本)9781457713989

The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to automatically synthesize hardware accelerators from OpenCL applications. OpenCL is a recent industry supported standard for writing programs that execute on multicore platforms and accelerators such as GPUs. Our methodology maps OpenCL kernels into hardware accelerators, based on architectural templates that explicitly decouple computation from memory communication whenever this is possible. The templates can be tuned to provide a wide repertoire of accelerators that meet user performance requirements and FPGA device characteristics. Furthermore, a set of high- and low-level compiler optimizations is applied to generate optimized accelerators. Our experimental evaluation shows that the generated accelerators are tuned efficiently to match the applications memory access pattern and computational complexity, and to achieve user performance requirements. An important objective of our tool is to expand the FPGA development user base to software engineers, thereby expanding the scope of FPGAs beyond the realm of hardware design.

关键词： Kernel Hardware Field programmable gate arrays Synchronization Computational modeling Pipelines Optimization

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Benchmarking SciDB data import on HPC systems

Benchmarking SciDB data import on HPC systems

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IEEE conference on High Performance Extreme Computing (HPEC)

作者： Siddharth Samsi Laura Brattain William Arcand David Bestor Bill Bergeron Chansup Byun Vijay Gadepally Matthew Hubbell Michael Jones Anna Klein Peter Michaleas Lauren Milechin Julie Mullen Andrew Prout Antonio Rosa Charles Yee Jeremy Kepner Albert Reuther MIT Lincoln Laboratory Lexington MA Massachusetts Institute of Technology Lincoln Laboratory Lexington MA US

ISBN: (纸本)9781509035267

SciDB is a scalable, computational database management system that uses an array model for data storage. The array data model of SciDB makes it ideally suited for storing and managing large amounts of imaging data. SciDB is designed to support advanced analytics in database, thus reducing the need for extracting data for analysis. It is designed to be massively parallel and can run on commodity hardware in a high performance computing (HPC) environment. In this paper, we present the performance of SciDB using simulated image data. The Dynamic Distributed Dimensional Data Model (D4M) software is used to implement the benchmark on a cluster running the MIT SuperCloud software stack. A peak performance of 2.2M database inserts per second was achieved on a single node of this system. We also show that SciDB and the D4M toolbox provide more efficient ways to access random sub-volumes of massive datasets compared to the traditional approaches of reading volumetric data from individual files. This work describes the D4M and SciDB tools we developed and presents the initial performance results. This performance was achieved by using parallel inserts, a in-database merging of arrays as well as supercomputing techniques, such as distributed arrays and single-program-multiple-data programming.

关键词： Arrays Databases Data models parallel processing Imaging Software Engines

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Java and the Power of Multi-Core Processing

Java and the Power of Multi-Core Processing

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2nd International conference on Complex, Intelligent and Software Intensive Systems (CISIS 2008)

作者： Peter Bertels Dirk Stroobandt ELIS Department Ghent University Belgium Belgium ELIS Department Ghent University Belgium

The new era of multi-core processing challenges software designers to efficiently exploit the parallelism that is now massively available. Programmers have to exchange the conventional sequential programming paradigm for parallel programming: single-threaded designs must be decomposed into dependent, interacting tasks. The Java programming language has built-in thread support and is therefore suitable for the development of parallel software, but programming multi-threaded applications is a tedious task. Therefore we are working on a framework and tool support to alleviate the burden of threads, synchronisation and locking, based on process networks. This paper describes our initial ideas for this new programming model.

关键词： Java Magnetic cores parallel processing Software parallel programming programming System recovery

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Design of the neural processor optimized for Xilinx Virtex FPGA devices

Design of the neural processor optimized for Xilinx Virtex F...

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International conference on Information Technology Interfaces

作者： J. Hudec M. Hust'ava Faculty of Electrical Engineering and Information Technology Department of Computer Science and Engineering Slovak University of Technology Bratislava Slovakia

ISBN: (纸本)9539676932

Focuses on the design of a parallel processor targeted at the rapid execution of neural networks. The basic architecture of the toroidal neural processor (TNP) is based on a toroidal mesh. This architecture was inspired by the need for a low-cost massively parallel processing system that could emulate a large variety of neural models. The TNP consists of two basic elements: a control unit and some processing units. The control unit acts as distributor of information and instructions for the processing units. The processing units perform exact operations on the data, based on the execution of instructions. The design of the TNP has a typical SIMD architecture. The processor has an enhanced interface with the host computer. This interface provides not only operations for programming and control of the TNP, but, in addition, any type of neural network and learning algorithm can be implemented through this interface. In the design of the TNP are implemented 10 control unit instructions and 11 processing unit instructions. The architecture of the TNP is optimized for Xilinx Virtex devices. The design uses many features of this family of FPGA devices. The VHDL constructs are mapped into hardware in the synthesis, optimization, place-and-route and implementation process. The optimization can significantly change the hardware that is generated. The TNP was tested, simulated and implemented in a Xilinx Foundation Technology Express version 3.3i environment with the Virtex XCV300 FPGA array and the HW-AFX-BG352-100 prototyping platform. The whole design can be implemented in Virtex E and Spartan devices too.

关键词： Design optimization Field programmable gate arrays Algorithm design and analysis Information technology Process design Neural networks Pipelines Design engineering parallel processing Computer architecture

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Firewall engine based on Graphics Processing Unit

Firewall engine based on Graphics Processing Unit

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International conference on Advanced Communication, Control and Computing Technologies (ICACCCT)

作者： Abhaya Kumar Sahoo Amardeep Das Mayank Tiwary Department of Information Technology C. V. Raman College of Engineering Bhubaneswar India

Firewalls are very important elements in network security. working of firewall rules for enterprise network has become complex, error-prone and time-consuming. Firewall filtering rules have to be carefully written and organized in order to correctly implement the security policy. The main issue is the slow filtering action during heavy load. To reduce the time consumption there is a very urgent need of optimized firewall engine, which runs on GPU's. We mainly focus on the creating parallel algorithms for desktop firewall which reduces the time consumption and at the same time it can allow for strong threat detection, intrusion detection of incoming packets. In our paper we have created parallel optimized algorithms for intrusion detection, threat detection, packet filtering and network address translation which runs on NVIDIA's GPU card and it is based on CUDA programming. For our experimental analysis, we have created test packets and for virus scanning we have used the virus-signatures from Clam-AV.

关键词： Graphics processing units Computational modeling Random access memory Analytical models Instruction sets Filtering algorithms Performance evaluation

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Benchmarking Thread Block Cluster

Benchmarking Thread Block Cluster

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IEEE conference on High Performance Extreme Computing (HPEC)

作者： Tim Lühnen Tobias Marschner Sohan Lal Massively Parallel Systems Group Hamburg University of Technology Hamburg Germany

ISBN: (数字)9798350387131

ISBN: (纸本)9798350387148

Graphics processing units (GPUs) have become essential accelerators in the fields of artificial intelligence (AI), high performance computing (HPC), and data analytics, offering substantial performance improvements over traditional computing resources. In 2022, NVIDIA's release of the Hopper architecture marked a significant advancement in GPU design by adding a new hierarchical level to their CUDA programming model: the thread block cluster (TBC). This feature enables the grouping of thread blocks, facilitating direct communication and synchronization between them. To support this, a dedicated SM-to-SM network was integrated, connecting streaming multiprocessors (SMs) to facilitate efficient inter-block communication. This paper delves into the performance characteristics of this new feature, specifically examining the latencies developers can anticipate when utilizing the direct communication channel provided by TBCs. We present an analysis of the SM-to-SM network behavior, which is crucial for developing accurate analytical and cycle-accurate simulation models. Our study includes a comprehensive evaluation of the impact of TBCs on application performance, highlighting scenarios where this feature can lead to significant improvements. For instance, applications where a data-producing thread block writes data directly into the shared memory of the consuming thread block can be up to 2.3x faster than using global memory for data transfer. Additionally, applications constrained by shared memory can achieve up to a 2.1x speedup by employing TBCs. Our findings also reveal that utilizing large cluster dimensions can result in an execution time overhead exceeding 20%. By exploring the intricacies of the Hopper architecture and its new TBC feature, this paper equips developers with the knowledge needed to harness the full potential of modern GPUs and assists researchers in developing accurate analytical and cycle-accurate simulation models.

关键词： Analytical models Accuracy Instruction sets Computational modeling Graphics processing units Benchmark testing Data transfer Synchronization Resource management Artificial intelligence

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Production grid systems and their programming 11th

引用

11th European conference on parallel Virtual Machine and Message Passing Interface Users Group Meeting, PVM/MPI 2004

作者： Kacsuk, Péter Kónya, Balázs Stefán, Péter MTA-SZTAKI Kende str. 13-17 BudapestH-1111 Hungary Lund University Department of Experimental High Energy Physics P.O.Box 118 LundSE-22100 Sweden NIIF/HUNGARNET Victor Hugo str. 18-22 BudapestH-1132 Hungary

ISBN: (纸本)3540231633

There are a large variety of Grid test-beds that can be used for experimental purposes by a small community. However, the number of production Grid systems that can be used as a service for a large community is very limited. The current tutorial provides introduction to three of these very few production Grid systems. They represent different models and policies of using Grid resources and hence understanding and comparing them is an extremely useful exercise to everyone interested in Grid technology The Hungarian ClusterGrid infrastructure connects clusters during the nights and weekends. These clusters are used during the day for educational purposes at the Hungarian universities and polytechnics. Therefore a unique feature of this Grid the switching mechanism by which the day time and night time working modes are loaded to the computers. In order to manage the system as a production one the system is homogeneous, all the machines should install the same Grid software package. The second even larger production Grid system is the LHC-Grid that was developed by CERN to support the Large Hydron Collider experiments. This Grid is also homogeneous but it works as a 24-hour service. All the computers in the Grid are completely devoted to offer Grid services. The LHC-Grid is mainly used by physists but in the EGEE project other applications like bio-medical applications will be ported and supported on this Grid. The third production Grid is the NorduGrid which is completely heterogeneous and the resources can join and leave the Grid at any time as they need. The NorduGrid was developed to serve the Nordic countries of Europe but now more and more institutions from other countries join this Grid due to its large flexibility. Concerning the user view an important question is how to handle this large variety of production Grids and other Grid test-beds. How to develop applications for such different Grid systems and how to port applications among them? A possible answer for

关键词： Equipment testing

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DiCE: Distributed Code Generation and Execution

DiCE: Distributed Code Generation and Execution

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Pervasive and Intelligent Computing (PICom), IEEE conference on

作者： Kunal Rao Giuseppe Coviello Srimat Chakradhar NEC Laboratories America Princeton NJ

ISBN: (数字)9798331522742

ISBN: (纸本)9798331522759

Generative artificial intelligence (GenAI), specifically, Large Language models (LLMs), have shown tremendous potential in automating several tasks and improving human productivity. Recent works have shown them to be quite useful in writing and summarizing text (articles, blogs, poems, stories, songs, etc.), answering questions, brainstorming ideas, and even writing code. Several LLMs have emerged specifically targeting code generation. Given a prompt, these LLMs can generate code in any desired programming language. Many tools like ChatGPT, CoPilot, CodeWhisperer, Cody, DeepSeek Coder, StarCoder, etc. are now routinely being used by software developers. However, most of the prior work in automatic code generation using LLMs is focused on obtaining “correct” and working code, and mainly runs on a single computer (serial code). In this paper, we take this to the next level, where LLMs are leveraged to generate code for execution on a distributed infrastructure. We propose a novel system called DiCE, which takes serial code as input and automatically generates distributed version of the code and efficiently executes it on a distributed setup. DiCE consists of two main components (a) LLM-based tool (Synthia) to understand dependencies in serial code and automatically generate distributed version of the code using specialized programming model and semantics, and (b) Runtime (Hermod) to understand the semantics in the distributed code and realize efficient execution on a cluster of machines (distributed infrastructure). DiCE currently focuses on visual programs synthesized by tools like ViperGPT [1] and VisReP [2] (serial code), automatically identifies higher-level task parallelism opportunities (e.g., parallel object detection), transforms the code to exploit the parallelism, and finally efficiently executes it on a cluster of machines. Through our experiments using 100 examples from the GQA dataset [3], we show that the serial codes generated by ViperGPT are successfu

关键词： Visualization Codes Runtime Generative AI Semantics Transforms parallel processing Writing programming Software

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Using Global Behavior Modeling to Improve QoS in Cloud Data Storage Services

Using Global Behavior Modeling to Improve QoS in Cloud Data ...

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IEEE International conference on Cloud Computing Technology and Science (CloudCom)

作者： Jesus Montes Bogdan Nicolae Gabriel Antoniu Alberto Sánchez María S Pérez Universidad Politécnica de Madrid Madrid Spain University of Rennes 1 IRISA Rennes France INRIA Rennes Bretagne Atlantique Rennes France Universidad Rey Juan Carlos Madrid Spain

The cloud computing model aims to make large-scale data-intensive computing affordable even for users with limited financial resources, that cannot invest into expensive infrastructures necesssary to run them. In this context, MapReduce is emerging as a highly scalable programming paradigm that enables high-throughput data-intensive processing as a cloud service. Its performance is highly dependent on the underlying storage service, responsible to efficiently support massively parallel data accesses by guaranteeing a high throughput under heavy access concurrency. In this context, quality of service plays a crucial role: the storage service needs to sustain a stable throughput for each individual accesss, in addition to achieving a high aggregated throughput under concurrency. In this paper we propose a technique to address this problem using component monitoring, application-side feedback and behavior pattern analysis to automatically infer useful knowledge about the causes of poor quality of service and provide an easy way to reason in about potential improvements. We apply our proposal to Blob Seer, a representative data storage service specifically designed to achieve high aggregated throughputs and show through extensive experimentation substantial improvements in the stability of individual data read accesses under MapReduce workloads.

关键词： Monitoring Throughput Data models Computational modeling Context Quality of service Stability analysis

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