The paper proposes and analyzes a scalable model of an associative distributed shared memory for massivelyparallel architectures. The proposed model is hierarchical and fits the modern style of structured parallel pr...
详细信息
The paper proposes and analyzes a scalable model of an associative distributed shared memory for massivelyparallel architectures. The proposed model is hierarchical and fits the modern style of structured parallelprogramming. If parallel applications are composed of a set of modules with a well-defined scope of interaction, the proposed model can induce a memory access latency time that only logarithmically increases with the number of nodes. Experimental results show the effectiveness of the model with a transputer-based implementation.
We describe Actors, a flexible, scalable and efficient model of computation, and develop a framework for analyzing the parallel complexity of programs written in it. Actors are asynchronous, autonomous objects which i...
详细信息
In this paper, we investigate the suitability of parallel architectures for the realization of a novel object-based computational model encapsulated within programming languages such as [11]. This model incorporates o...
详细信息
In this paper, we investigate the suitability of parallel architectures for the realization of a novel object-based computational model encapsulated within programming languages such as [11]. This model incorporates objects, groups, broadcast message-passing and asynchronous execution. As such it provides a high-level, architecture-independent representation for a variety of concurrent systems. The class of parallel architectures which we consider are logically shared but physically distributed memory systems.
Research in the use of DEVS (Discrete Event System Specification) based representation of large models on massivelyparallel platforms is summarized here. We show that parallel DEVS-representation of large scale model...
详细信息
ISBN:
(纸本)0819424986
Research in the use of DEVS (Discrete Event System Specification) based representation of large models on massivelyparallel platforms is summarized here. We show that parallel DEVS-representation of large scale models can achieve several orders of magnitude speedup. When mapped onto distributed memory multicomputer systems, additional speedup is obtained. An example of a watershed simulation is presented which has been executed in the DEVS-C++/MPI environment working on the CM-5 and IBM SP2 massivelyparallel systems.
In this talk we present the intrinsic connection between modelling the suitable data type by algebraic specification and the correct and efficient implementation of high-speed parallel algorithms in hardware or softwa...
详细信息
In this talk we present the intrinsic connection between modelling the suitable data type by algebraic specification and the correct and efficient implementation of high-speed parallel algorithms in hardware or software. The design tool IDEAS developed at the author's institution representing the first such instrument for automatic parallel algorithm generation is described.
Functions that invoke operations on multiple objects atomically are a useful extension of object-based parallel languages, such as Orca. This paper introduces atomic functions and shows how compile-time information ca...
详细信息
Functions that invoke operations on multiple objects atomically are a useful extension of object-based parallel languages, such as Orca. This paper introduces atomic functions and shows how compile-time information can drive run-time optimizations of such functions.
A-NETL is a parallel object-oriented language intended to be used for managing small to massive parallelism with medium grain size. Its design goals are to support various styles of message passing, to treat data para...
详细信息
A-NETL is a parallel object-oriented language intended to be used for managing small to massive parallelism with medium grain size. Its design goals are to support various styles of message passing, to treat data parallel operations at the same cost as programming languages of the SIMD type, to provide several synchronization facilities for autonomous control, and to provide information for the efficient allocation of objects to nodes. Starting with these design principles, this paper then goes on to describe the syntax and semantics of the language and the major implementation issues, including the reduction of message communication cost, efficient implementation of statically and dynamically created massive objects, the realization of synchronization schemes, the object-to-node allocation scheme to minimize communication cost, and logical-time-based debugging for asynchronous operations.
Various parallel Fortran languages have been developed over the years. The research work in creating this parallel Fortran Family has made significant contributions to parallelprogramming language design and implemen...
详细信息
Various parallel Fortran languages have been developed over the years. The research work in creating this parallel Fortran Family has made significant contributions to parallelprogramming language design and implementation. In this paper, various parallel Fortran languages are studied based on a uniform co-ordination approach towards parallelprogramming. That is, new language constructs in parallel Fortran systems are regarded as providing a co-ordination mechanism organizing a set of single-threaded computations, coded in standard Fortran, into a parallel ensemble. Features of different parallel Fortran languages are studied by investigating their corresponding co-ordination models. A new perspective on designing a structured parallel Fortran system is proposed by using a generic structured co-ordination language, SCL, as the uniform means to organize parallel Fortran computation.
SVM-Fortran is a language designed to program highly parallel systems with a global address space. A compiler for SVM-Fortran is described which generates code for parallel machines;our current target machine is the I...
详细信息
SVM-Fortran is a language designed to program highly parallel systems with a global address space. A compiler for SVM-Fortran is described which generates code for parallel machines;our current target machine is the Intel Paragon XP/S with an SVM-extension called ASVM. Performance numbers are given for applications and compared to results obtained with corresponding HPF-versions.
In this paper we show how edge addition rewrite systems (EARS) can be evaluated in parallel. EARS are a simple variant of graph rewrite systems, which only add edges to graphs. Because EARS are equivalent to a subset ...
详细信息
In this paper we show how edge addition rewrite systems (EARS) can be evaluated in parallel. EARS are a simple variant of graph rewrite systems, which only add edges to graphs. Because EARS are equivalent to a subset of Datalog, they provide a programming model for rule-based applications. EARS terminate and are strongly confluent, which makes them perfectly apt for parallel execution. In this paper we present two parallel evaluation methods, order-domain partitioning and evaluation on carrier-graphs. Because also efficient sequential evaluation techniques exist, EARS provide scalable parallelism.
暂无评论