检索结果-内蒙古大学图书馆

Code Complexity versus Performance for GPU-accelerated Scientific applications

Code Complexity versus Performance for GPU-accelerated Scien...

International workshop on Software Engineering for High Performance computing in Computational Science & Engineering (SE-HPCCSE)

作者： A WK. Umayanganie Munipala Shirley V. Moore University of Texas at El Paso 500 West University Avenue El Paso TX Oak Ridge National Laboratory Oak Ridge TN

ISBN: (纸本)9781509052257

Summary form only given. Graphics Processing Units (GPUs) are becoming widely used as parallel accelerators in high-performance computing. GPU programming until recently, has been done by using low-level programming models such as CUDA and OpenCL. The directive-based OpenACC programming model has been growing in popularity due to its higher level of abstraction. This technique, which uses “directive” or “pragma” statements to annotate source code written in traditional high-level languages such as Fortran, C, and C++, is intended to allow a single code base to work across multiple computational platforms. We attempt to compare code complexity and performance of CUDA, OpenCL, and OpenACC implementations for three benchmark codes - the Game of Life (GOL) example code, the LULESH hydrodynamics proxy application, and the CloverLeaf mini-app from the Mantevo suite For the GOL C, CUDA C, and OpenCL codes and the LULESH C++, CUDA, and OpenCL codes, we measured source lines of code (SLOC) and cyclomatic complexity using the Oxbow toolkit static analysis tools. We ran the commercial McCabe IQ tool on the CloverLeaf Fortran90, Fortran90 + OpenACC, and Fortran portion of CloverLeaf_CUDA to measure cyclomatic complexity, design complexity, and essential complexity. We found that the CUDA and OpenCL implementations have significantly more lines of code than the corresponding OpenACC implementations but that the measured cyclomatic complexity is not always higher. The CUDA and OpenCL implementations generally have better performance, but there is not a drastic difference if the OpenACC code is optimized. We conclude that the available metrics and tools for measuring complexity of GPU programs are inadequate, since they do not quantify the portability and maintainability of the codes, and that specialization and extensions are needed.

关键词： Complexity theory Graphics processing units programming Measurement Software engineering Computational modeling C++ languages

来源：评论

学校读者我要写书评

暂无评论

programming GRAPHICS PROCESSING UNITS IN THE RVC-CAL DATAFLOW LANGUAGE

PROGRAMMING GRAPHICS PROCESSING UNITS IN THE RVC-CAL DATAFLO...

引用

IEEE International workshop on Signal Processing Systems (SiPS)

作者： Boutellier, J. Nylanden, T. Univ Oulu Dept Comp Sci & Engn Oulu Finland

ISBN: (纸本)9781467396042

The interest towards programming of streaming applications using dataflow models of computation has been increasing steadily in the recent years. Among the numerous dataflow formalisms, the ISO-standardized RVC-CAL dataflow language has offered a solid basis for programming tool development and research. To this date RVC-CAL programming tools have enabled transforming dataflow programs into concurrent executables for multicore processors, as well as for generating synthesizable hardware descriptions. In this paper it is shown how the RVC-CAL dataflow language can be used for programming graphics processing units (GPUs) with high efficiency. Considering the processing architectures of recent mobile and desktop computing devices, this advance is of high importance, as most consumer devices contain a graphics processing unit nowadays. To evaluate the proposed solution, the paper presents a video processing application case study. At best, the solution is shown to provide a speedup of 42x over single-threaded CPU execution.

关键词： Dataflow computing design automation parallel processing

来源：评论

学校读者我要写书评

暂无评论

Enhancing productivity and performance portability of OpenCL applications on heterogeneous systems using runtime optimizations

Enhancing productivity and performance portability of OpenCL...

引用

作者： Lutz, Thibaut University of Edinburgh

学位级别：doctor

Initially driven by a strong need for increased computational performance in science and engineering, heterogeneous systems have become ubiquitous and they are getting increasingly complex. The single processor era has been replaced with multi-core processors, which have quickly been surrounded by satellite devices aiming to increase the throughput of the entire system. These auxiliary devices, such as Graphics Processing Units, Field Programmable Gate Arrays or other specialized processors have very different architectures. This puts an enormous strain on programming models and software developers to take full advantage of the computing power at hand. Because of this diversity and the unachievable flexibility and portability necessary to optimize for each target individually, heterogeneous systems remain typically vastly under-utilized. In this thesis, we explore two distinct ways to tackle this problem. Providing automated, non intrusive methods in the form of compiler tools and implementing efficient abstractions to automatically tune parameters for a restricted domain are two complementary approaches investigated to better utilize compute resources in heterogeneous systems. First, we explore a fully automated compiler based approach, where a runtime system analyzes the computation flow of an OpenCL application and optimizes it across multiple compute kernels. This method can be deployed on any existing application transparently and replaces significant software engineering effort spent to tune application for a particular system. We show that this technique achieves speedups of up to 3x over unoptimized code and an average of 1.4x over manually optimized code for highly dynamic applications. Second, a library based approach is designed to provide a high level abstraction for complex problems in a specific domain, stencil computation. Using domain specific techniques, the underlying framework optimizes the code aggressively. We show that even in a restricted doma

关键词： GPGPU General-Purpose computing on Graphics Processing Unit Open Compute Language OpenCL complier staging

来源：评论

学校读者我要写书评

暂无评论

Improvement on the Method for Automatic Differential Analysis and Its application to Two Lightweight Block Ciphers DESL and LBlock-s 10th

Improvement on the Method for Automatic Differential Analysi...

引用

10th International workshop on Security (IWSEC)

作者： Sun, Siwei Hu, Lei Qiao, Kexin Ma, Xiaoshuang Shan, Jinyong Song, Ling Chinese Acad Sci Inst Informat Engn State Key Lab Informat Secur Beijing 100093 Peoples R China Chinese Acad Sci Data Assurance & Commun Secur Res Ctr Beijing 100093 Peoples R China

ISBN: (纸本)9783319224251;9783319224244

With the development of the ubiquitous computing and large-scale information processing systems, the demand for lightweight block ciphers which is suitable for resource constrained computing devices is increasing. Hence, the methodology for design and analysis of block ciphers is becoming more important. In this paper, we use the Mixed-Integer Linear programming (MILP) based tools for automatic differential cryptanalysis in a clever way to find improved single-key and related-key differential characteristics for DESL (a lightweight variant of the well known Data Encryption Standard), and obtain tighter security bound for LBlock-s (a core component of an lightweight authenticated encryption algorithm submitted to the international competition for authenticated encryption -CAESAR) against related-key differential attack. To be more specific, in searching for improved characteristics, we restrict the differential patterns allowed in the first and last rounds of the characteristics in the feasible region of an MILP problem by imposing different constraints than other rounds, and we partition the differential patterns of the DESL S-box into different sets with 2-bit more information associated with each pattern according to their probabilities. In addition, we show how to use the Gurobi optimizer combined with a known good characteristic to speed up the characteristic searching and bound proving process. Using these techniques, we managed to find the currently known best 9-round related-key differential characteristic for DESL, and the first published nontrivial related-key and single-key differential characteristics covering 10 rounds of DESL. Also, we obtain the currently known tightest security bound for LBlock-s against related-key differential attack. These techniques should be useful in analysis and design of other lightweight block ciphers.

关键词： Automatic cryptanalysis Security evaluation Related-key differential attack Authenticated encryption Mixed-Integer Linear programming

来源：评论

学校读者我要写书评

暂无评论

programming graphics processing units in the RVC-CAL dataflow language

Programming graphics processing units in the RVC-CAL dataflo...

引用

IEEE workshop on Signal Processing Systems (SIPS)

作者： J. Boutellier T. Nylanden Dept. of Computer Science and Engineering University of Oulu Finland

关键词： programming Graphics processing units Ports (Computers) Computational modeling Parallel processing Generators

来源：评论

学校读者我要写书评

暂无评论

Parallel architecture benchmarking: from embedded computing to HPC, a FiPS project perspective 12

Parallel architecture benchmarking: from embedded computing ...

引用

12th IEEE/IFIP International Conference on Embedded and ubiquitous computing (EUC)

作者： Lhuillier, Yves Philippe, Jean-Marc Guerre, Alexandre Kierzynka, Michal Oleksiak, Ariel CEA Saclay Nano INNOV Inst CARNOT CEA LIST F-91191 Gif Sur Yvette France Poznan Supercomp & Networking Ctr PL-61704 Poznan Poland Poznan Univ Tech PL-60965 Poznan Poland

ISBN: (纸本)9780769552491

With the growing numbers of both parallel architectures and related programming models, the benchmarking tasks become very tricky since parallel programming requires architecture-dependent compilers and languages as well as high programming expertise. More than just comparing architectures with synthetic benchmarks, benchmarking is also more and more used to design specialized systems composed of heterogeneous computing resources to optimize the performance or performance/watt ratio (e.g. embedded systems designers build Systemon-Chip (SoC) out of dedicated and well-chosen components). In the High-Perfomance-computing (HPC) domain, systems are designed with symmetric and scalable computing nodes built to deliver the highest performance on a wide variety of applications. However, HPC is now facing cost and power consumption issues which motivate the design of heterogeneous systems. This is one of the rationales of the European FiPS project, which proposes to develop hardware architecture and software methodology easing the design of such systems. Thus, having a fair comparison between architectures while considering an application is of growing importance. Unfortunately, porting it on all available architectures using the related programming models is impossible. To tackle this challenge, we introduced a novel methodology to evaluate and to compare parallel architectures in order to ease the work of the programmer. Based on the usage of microbenchmarks, code profiling and characterization tools, this methodology introduces a semi-automatic prediction of sequential applications performances on a set of parallel architectures. In addition, performance estimation is correlated with the cost of other criteria such as power or portability effort. Introduced for targeting vision-based embedded applications, our methodology is currently being extended to target more complex applications from HPC world. This paper extends our work with new experiments and early results on a

关键词： embedded systems parallel architectures performance evaluation system-on-chip European FiPS project FiPS project perspective HPC SoC System-on-Chip architecture dependent compilers embedded computing embedded systems designers hardware architecture high performance computing parallel architecture benchmarking performance estimation related programming models scalable computing nodes software methodology symmetric computing nodes synthetic benchmarks Benchmark testing Computer architecture Databases Hardware Kernel programming Servers Benchmarking Bioinformatics computing servers Heterogeneity High Performance computing Parallel architectures system-on-chip Embedded computing Performance Evaluation BENCHMARKS hardware architecture Benchmark testing Embedded systems programming Computer Architecture Servers Computer hardware Bioinformatics Database

来源：评论

学校读者我要写书评

暂无评论

A HLS-based toolflow to design next-generation heterogeneous many-core platforms with shared memory 12

A HLS-based toolflow to design next-generation heterogeneous...

引用

12th IEEE/IFIP International Conference on Embedded and ubiquitous computing (EUC)

作者： Burgio, Paolo Marongiu, Andrea Coussy, Philippe Benini, Luca Univ Bretagne Sud LabSTICC Lorient France Univ Bologna DEI I-40126 Bologna Italy Swiss Fed Inst Technol Integrated Syst Lab Zurich Switzerland

ISBN: (纸本)9780769552491

This work describes how we use High-Level Synthesis to support design space exploration (DSE) of heterogeneous many-core systems. Modern embedded systems increasingly couple hardware accelerators and processing cores on the same chip, to trade specialization of the platform to an application domain for increased performance and energy efficiency. However, the process of designing such a platform is complex and error-prone, and requires skills on algorithmic aspects, ardware synthesis, and software engineering. DSE can partially be automated, and thus simplified, by coupling the use of HLS tools and virtual prototyping platforms. In this paper we enable the design space exploration of heterogeneous many-cores adopting a shared-memory architecture template, where communication and synchronization between the hardware accelerators and the cores happens through L1 shared memory. This communication infrastructure leverages a "zero-copy" scheme, which simplifies both the design process of the platform and the development of applications on top of it. Moreover, the shared-memory template perfectly fits the semantics of several high-level programming models, such as OpenMP. We provide programmers with simple yet powerful abstractions to exploit accelerators from within an OpenMP application, and propose a low-cost implementation of the necessary runtime support. An HLS-based automatic design flow is set up, to quickly explore the design space using a cycle-accurate virtual platform.

关键词： embedded systems parallel programming shared memory systems DSE HLS-based toolflow L1 shared memory OpenMP application cycle-accurate virtual platform design space exploration high-level programming models high-level synthesis modern embedded systems next-generation heterogeneous many-core platforms shared-memory architecture template Acceleration Computer architecture Hardware Program processors programming Registers Synchronization OpenMP clustered architectures heterogeneous architectures hls many-core systems shared-memory systems Embedded systems shared memory systems high level synthesis Space Exploration DSE gene Program processors Computer Architecture Registers Parallel programming shared memory Computer hardware programming hardware accelerator Platform acceleration

来源：评论

学校读者我要写书评

暂无评论

Parallel Architecture Benchmarking: From Embedded computing to HPC, a FiPS Project Perspective

Parallel Architecture Benchmarking: From Embedded Computing ...

引用

IEEE/IFIP International Conference on Embedded and ubiquitous computing, EUC

作者： Yves Lhuillier Jean Marc Philippe Alexandre Guerre Michal Kierzynka Ariel Oleksia CEA Saclay Nano-INNOV Institut CARNOT CEA LIST Gif sur Yvette France Poznań Supercomputing and Networking Center Poznań Poland Poznań University of Technology Poznań Poland Poznan Supercomput. & Networking Center Poznań Poland

With the growing numbers of both parallel architectures and related programming models, the benchmarking tasks become very tricky since parallel programming requires architecture-dependent compilers and languages as well as high programming expertise. More than just comparing architectures with synthetic benchmarks, benchmarking is also more and more used to design specialized systems composed of heterogeneous computing resources to optimize the performance or performance/watt ratio (e.g. embedded systems designers build System-on-Chip (SoC) out of dedicated and well-chosen components). In the High-Performance-computing (HPC) domain, systems are designed with symmetric and scalable computing nodes built to deliver the highest performance on a wide variety of applications. However, HPC is now facing cost and power consumption issues which motivate the design of heterogeneous systems. This is one of the rationales of the European FiPS project, which proposes to develop hardware architecture and software methodology easing the design of such systems. Thus, having a fair comparison between architectures while considering an application is of growing importance. Unfortunately, porting it on all available architectures using the related programming models is impossible. To tackle this challenge, we introduced a novel methodology to evaluate and to compare parallel architectures in order to ease the work of the programmer. Based on the usage of micro benchmarks, code profiling and characterization tools, this methodology introduces a semi-automatic prediction of sequential applications performances on a set of parallel architectures. In addition, performance estimation is correlated with the cost of other criteria such as power or portability effort. Introduced for targeting vision-based embedded applications, our methodology is currently being extended to target more complex applications from HPC world. This paper extends our work with new experiments and early results on

关键词： Kernel Computer architecture Databases Benchmark testing programming Hardware Servers

来源：评论

学校读者我要写书评

暂无评论

A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory

A HLS-Based Toolflow to Design Next-Generation Heterogeneous...

引用

IEEE/IFIP International Conference on Embedded and ubiquitous computing, EUC

作者： Paolo Burgio Andrea Marongiu Philippe Coussy Luca Benini DEI Università degli Studi di Bologna Italy LabSTICC Université de Bretagne-Sud France Integrated Systems Laboratory ETH Zurich Switzerland

This work describes how we use High-Level Synthesis to support design space exploration (DSE) of heterogeneous many-core systems. Modern embedded systems increasingly couple hardware accelerators and processing cores on the same chip, to trade specialization of the platform to an application domain for increased performance and energy efficiency. However, the process of designing such a platform is complex and error-prone, and requires skills on algorithmic aspects, hardware synthesis, and software engineering. DSE can partially be automated, and thus simplified, by coupling the use of HLS tools and virtual prototyping platforms. In this paper we enable the design space exploration of heterogeneous many-cores adopting a shared-memory architecture template, where communication and synchronization between the hardware accelerators and the cores happens through L1 shared memory. This communication infrastructure leverages a "zero-copy" scheme, which simplifies both the design process of the platform and the development of applications on top of it. Moreover, the shared-memory template perfectly fits the semantics of several high-level programming models, such as OpenMP. We provide programmers with simple yet powerful abstractions to exploit accelerators from within an OpenMP application, and propose a low-cost implementation of the necessary runtime support. An HLS-based automatic design flow is set up, to quickly explore the design space using a cycle-accurate virtual platform.

关键词： Acceleration programming Program processors Hardware Computer architecture Registers Synchronization

来源：评论

学校读者我要写书评

暂无评论

Building ubiquitous QoC-aware applications through model-driven software engineering

引用

SCIENCE OF COMPUTER programming 2013年第10期78卷 1912-1929页

作者： Chabridon, Sophie Conan, Denis Abid, Zied Taconet, Chantal TELECOM SudParis Inst TELECOM CNRS UMR Samovar F-91011 Evry France

As every-day mobile devices can easily be equipped with multiple sensing capabilities, ubiquitous applications are expected to exploit the richness of the context information that can be collected by these devices in order to provide the service that is the most appropriate to the situation of the user. However, the design and implementation of such context-aware ubiquitous appplications remain challenging as there exist very few models and tools to guide application designers and developers in mastering the complexity of context information. This becomes even more crucial as context is by nature imperfect. One way to address this issue is to associate to context information meta-data representing its quality. We propose a generic and extensible design process for context-aware applications taking into account the quality of context (QoC). We demonstrate its use on a prototype application for sending flash sale offers to mobile users. We present extensive performance results in terms of memory and processing time of both elementary context management operations and the whole context policy implementing the Flash sale application. The cost of adding QoC management is also measured and appears to be limited to a few milliseconds. We show that a context policy with 120 QoC-aware nodes can be processed in less than 100 ms on a mobile phone. Moreover, a policy of almost 3000 nodes can be instantiated before exhausting the resources of the phone. This enables very rich application scenarios enhancing the user experience and will favor the development of new ubiquitous applications. (C) 2012 Elsevier B.V. All rights reserved.

关键词： Model-driven software engineering Context Quality of context Domain specific language ubiquitous computing Pervasive computing

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：