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Annual IEEE Northeast workshop on circuits and Systems (NEWCAS)

作者： Marwan Kanaan Roni Khazaka Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

The simulation of Radio Frequency circuits can be very CPU expensive due to the large number of equations present as well as the density of the Jacobian matrix. This problem becomes even more pronounced when simulating a system containing multiple circuits. In this paper a model order reduction method is proposed for obtaining a reduced order nonlinear macromodel for an RF circuit block. This macromodel can then be efficiently used in an overall system simulation.

关键词： Integrated circuit modeling Mathematical model Harmonic analysis Equations Load modeling Power generation Computational modeling

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MOS transistor mismatch modelling for high voltage CMOS processes

MOS transistor mismatch modelling for high voltage CMOS proc...

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IEEE/SEMI Conference and workshop on Advanced Semiconductor Manufacturing

作者： W. Posch G. Rappitsch G. Leonardelli Process Characterisation Austria Microsystems AG Unterpremstatten Austria Design for Manufacturability Austria Microsystems AG Unterpremstatten Austria Yield Enhancement Austria Microsystems AG Unterpremstatten Austria

An algorithm is presented to extract device mismatch parameters for high voltage transistors. The mismatch parameters are determined in two steps. The device mismatch for the threshold voltage, the gain factor and the mobility reduction are extracted from a sensitivity model in saturation, whereas the extraction of the drift-resistance mismatch is carried out based on a MOS transistor model in the ohmic region. The extracted parameters are implemented as part of circuit simulation libraries to be used for Monte Carlo simulation. Production control parameters enable the monitoring of device mismatch for high voltage transistors

关键词： MOSFETs Semiconductor device modeling CMOS process Current measurement Threshold voltage Testing circuit simulation Libraries Parameter extraction Statistical analysis

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High-level area/delay/power estimation for low power system VLSIs with gated clocks

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2002年第4期E85A卷 827-834页

作者： Noda, S Togawa, N Yanagisawa, M Ohtsuki, T Waseda Univ Dept Elect Informat & Commun Engn Adv Res Inst Sci & Engn Tokyo 1698555 Japan Univ Kitakyushu Dept Informat & Media Sci Kitakyushu Fukuoka 8080135 Japan

At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating tradeoff between power and area/delay by applying gated clocks is very important. In this paper. we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.

关键词： high-level synthesis power estimation gated clock switching activity sequential circuit

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model-order reduction of VLSI circuit interconnects via a Laguerre representation

Model-order reduction of VLSI circuit interconnects via a La...

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IEEE workshop on Signal Propagation on Interconnects (SPI)

作者： M. Telescu N. Tanguy P. Brehonnet P. Vilbe L.C. Calvez F. Huret L. E. S. T.-UMR CNRS n°6165 Brest France

The VLSI (very large scale integration) industry has the tendency to decrease circuit size, increase speed, assuring ever lower energy consumption and ever higher integration density of analogical components accompanied by digital blocks. With this tendency circuit designers are faced with a new challenge: the analysis and modeling of logical and analogical signals propagating between two circuit points. The search for high speed applications makes the effects of interconnects, usually neglected in the past, an important issue; noise, delay, distortion, reflections and cross talk are just some of these effects. High integration density, miniaturization, high working frequencies are three great factors which prevent interconnects to be considered small independent circuits. Thus, simulation becomes a rather difficult task. Still, wouldn't it be possible to replace complete interconnect equivalent circuits by simpler and more flexible models. Our new model-order reduction technique is mainly based on the use of the Laguerre representation and a simple operator used to generate an approximation base.

关键词： Very large scale integration Integrated circuit interconnections Energy consumption Signal design Signal analysis circuit noise Delay effects Acoustic reflection Frequency circuit simulation

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Behavioural modelling Method for RF and Microwave Mixers

Behavioural Modelling Method for RF and Microwave Mixers

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International workshop on Integrated Nonlinear Microwave and Millimeterwave circuits, INMMIC

作者： F. J. Casas N. Garmendia J. Portilla Department of Electricity and Electronics University of Basque Country (UPV-EHU) Bilbao Spain

The use of behavioural models provide the required simulation agility to check-up the system performances. In this paper, a behavioural modelling approach for RF and microwave mixers is presented. The model consists in the series connection of an input LTI block and a nonlinear memory-less mixer block. This topology enable to reproduce transmission and mismatch effects at the input and output ports, providing accurate results both in time and frequency domain, with a significant reduction in terms of simulation time. The modelling technique is illustrated through a WLAN IEEE802.11a mixer circuit

关键词： Radio frequency Microwave theory and techniques circuit simulation Frequency domain analysis circuit topology Nonlinear filters Microwave filters Wireless LAN Nonlinear distortion Phase distortion

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Crosstalk Noise reduction Techniques Using SOI Substrate

Crosstalk Noise Reduction Techniques Using SOI Substrate

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Principles of Advanced and Distributed simulation (PADS), 2006 workshop on;Avignon,France

作者： Fargol Hasani Nasser Masoumi Behjat Forouzandeh School of ECE VLSI Research Laboratory University of Tehran Iran

As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques using Silicon On Insulator (SOI) substrate. Coupling through common silicon substrate has become an important limiting factor in high performance ICs. A study of the advantages of using SOI substrate in contrast to bulk is presented in this paper. Through MATLAB software, a system of three coupled wires is modeled as RC distributed networks. A resistive model is used to model both SOI and bulk substrates. The results are compared to the bulk in order to show the advantages of using SOI substrate to reduce crosstalk noise in deep sub micron technology.

关键词： Crosstalk Silicon on insulator technology Mathematical model Frequency Integrated circuit interconnections System performance Integrated circuit reliability Coupling circuits MATLAB Software systems

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A frequency domain approach for efficient model reduction of mixed VLSI circuits

A frequency domain approach for efficient model reduction of...

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IEEE workshop on Signal Propagation on Interconnects (SPI)

作者： A. Amghayrir P. Brehonnet N. Tanguy P. Vilbe L.C. Calvez F. Huret LEST-UBO UMR CNRS 6165 Brest France

It has become well accepted that interconnect delay dominates gate delay in current VLSI circuits. This paper introduces a new method, based on a frequency domain approach, for the simulation of interconnect problems ... 详细信息

关键词： Frequency domain analysis Reduced order systems Very large scale integration Integrated circuit interconnections Electromagnetic propagation Electromagnetic waveguides Dielectric substrates circuit simulation Context modeling Electromagnetic analysis

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A general method for multi-port active network reduction and realization

A general method for multi-port active network reduction and...

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IEEE International workshop on Behavioral modeling and simulation (BMAS)

作者： P. Liu Z. Qi A. Aviles S.X.-D. Tan Department of Electrical Engineering University of California Riverside CA USA

This paper presents a novel compact modeling technique for linear(ized) active analog circuits. The new method is based on a recently proposed general s-domain hierarchical modeling and analysis method. In this work, based on the characteristics of analog circuits, we propose a constrained linear least square based method to optimize the order reduced admittance matrices with respect to both magnitude and phase responses up to the given frequency range. Theoretically we show that the hierarchical reduction does not change the reciprocity property of the linear circuit. For analog active circuits, which typically are non-reciprocal, so do the order-reduced circuit admittance matrices after hierarchical reduction. We propose a novel general multi-port, non-reciprocal network realization method. The resulting modeling algorithm can take in the SPICE netlists of active circuits and generate high-fidelity compact macro models of the active circuits with easily controlled model accuracy and complexity. The experimental results on two low-pass active filters demonstrate effectiveness of the proposed algorithm.

关键词： Active circuits Radio frequency Analog circuits Admittance Active filters Integrated circuit interconnections Digital circuits Noise figure Least squares methods Constraint optimization

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Passive SVD Based model Order reduction with Parametric Port Formulation

Passive SVD Based Model Order Reduction with Parametric Port...

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IEEE workshop on Signal Propagation on Interconnects (SPI)

作者： Min Ma Roni Khazaka Department of Electrical and Computer Engineering McGill University Montreal Canada

In this paper, a passive multi-level model reduction method is presented, which is suitable for networks with large number of ports. By using prior information about the type of the loads that can be connected to the network, the congruence transformation matrix is chosen such that it minimizes the impact of the additional ports. Furthermore, an SVD based second level of reduction is utilized in order to address the inherent inefficiencies of Krylov subspaces. The reduced order macromodels obtained using the proposed method achieve significant CPU cost saving as is demonstrated in the examples

关键词： Integrated circuit interconnections Equations Frequency Voltage Telephony Reduced order systems Transmission line matrix methods Costs circuit simulation Distributed parameter circuits

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Generating Reduced Order models for High Speed VLSI Interconnects using Balancing-Free Square Root Method

Generating Reduced Order Models for High Speed VLSI Intercon...

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Principles of Advanced and Distributed simulation (PADS), 2006 workshop on;Avignon,France

作者： J. V. R. Ravindra M. B. Srinivas Center for VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad India

This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the availability of provable weighted error bounds for the reduced-order system. This paper shows that the balancing-free square root method produces reduced systems that accurately follow the time- and frequency- domain responses of the original system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed BSR achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature.

关键词： Reduced order systems Very large scale integration Integrated circuit interconnections RLC circuits Integrated circuit modeling Central Processing Unit Frequency Transfer functions Capacitance Transmission line matrix methods

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