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检索条件"任意字段=Workshop on Model Reduction for Circuit Simulation"
121 条 记 录,以下是91-100 订阅
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model order reduction for nonlinear macromodeling of RF circuits
Model order reduction for nonlinear macromodeling of RF circ...
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Annual IEEE Northeast workshop on circuits and Systems (NEWCAS)
作者: Marwan Kanaan Roni Khazaka Department of Electrical and Computer Engineering McGill University Montreal QUE Canada
The simulation of Radio Frequency circuits can be very CPU expensive due to the large number of equations present as well as the density of the Jacobian matrix. This problem becomes even more pronounced when simulatin... 详细信息
来源: 评论
MOS transistor mismatch modelling for high voltage CMOS processes
MOS transistor mismatch modelling for high voltage CMOS proc...
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IEEE/SEMI Conference and workshop on Advanced Semiconductor Manufacturing
作者: W. Posch G. Rappitsch G. Leonardelli Process Characterisation Austria Microsystems AG Unterpremstatten Austria Design for Manufacturability Austria Microsystems AG Unterpremstatten Austria Yield Enhancement Austria Microsystems AG Unterpremstatten Austria
An algorithm is presented to extract device mismatch parameters for high voltage transistors. The mismatch parameters are determined in two steps. The device mismatch for the threshold voltage, the gain factor and the... 详细信息
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High-level area/delay/power estimation for low power system VLSIs with gated clocks
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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2002年 第4期E85A卷 827-834页
作者: Noda, S Togawa, N Yanagisawa, M Ohtsuki, T Waseda Univ Dept Elect Informat & Commun Engn Adv Res Inst Sci & Engn Tokyo 1698555 Japan Univ Kitakyushu Dept Informat & Media Sci Kitakyushu Fukuoka 8080135 Japan
At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/de... 详细信息
来源: 评论
model-order reduction of VLSI circuit interconnects via a Laguerre representation
Model-order reduction of VLSI circuit interconnects via a La...
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IEEE workshop on Signal Propagation on Interconnects (SPI)
作者: M. Telescu N. Tanguy P. Brehonnet P. Vilbe L.C. Calvez F. Huret L. E. S. T.-UMR CNRS n°6165 Brest France
The VLSI (very large scale integration) industry has the tendency to decrease circuit size, increase speed, assuring ever lower energy consumption and ever higher integration density of analogical components accompani... 详细信息
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Behavioural modelling Method for RF and Microwave Mixers
Behavioural Modelling Method for RF and Microwave Mixers
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International workshop on Integrated Nonlinear Microwave and Millimeterwave circuits, INMMIC
作者: F. J. Casas N. Garmendia J. Portilla Department of Electricity and Electronics University of Basque Country (UPV-EHU) Bilbao Spain
The use of behavioural models provide the required simulation agility to check-up the system performances. In this paper, a behavioural modelling approach for RF and microwave mixers is presented. The model consists i... 详细信息
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Crosstalk Noise reduction Techniques Using SOI Substrate
Crosstalk Noise Reduction Techniques Using SOI Substrate
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Principles of Advanced and Distributed simulation (PADS), 2006 workshop on;Avignon,France
作者: Fargol Hasani Nasser Masoumi Behjat Forouzandeh School of ECE VLSI Research Laboratory University of Tehran Iran
As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a ... 详细信息
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A frequency domain approach for efficient model reduction of mixed VLSI circuits
A frequency domain approach for efficient model reduction of...
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IEEE workshop on Signal Propagation on Interconnects (SPI)
作者: A. Amghayrir P. Brehonnet N. Tanguy P. Vilbe L.C. Calvez F. Huret LEST-UBO UMR CNRS 6165 Brest France
It has become well accepted that interconnect delay dominates gate delay in current VLSI circuits. This paper introduces a new method, based on a frequency domain approach, for the simulation of interconnect problems ... 详细信息
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A general method for multi-port active network reduction and realization
A general method for multi-port active network reduction and...
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IEEE International workshop on Behavioral modeling and simulation (BMAS)
作者: P. Liu Z. Qi A. Aviles S.X.-D. Tan Department of Electrical Engineering University of California Riverside CA USA
This paper presents a novel compact modeling technique for linear(ized) active analog circuits. The new method is based on a recently proposed general s-domain hierarchical modeling and analysis method. In this work, ... 详细信息
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Passive SVD Based model Order reduction with Parametric Port Formulation
Passive SVD Based Model Order Reduction with Parametric Port...
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IEEE workshop on Signal Propagation on Interconnects (SPI)
作者: Min Ma Roni Khazaka Department of Electrical and Computer Engineering McGill University Montreal Canada
In this paper, a passive multi-level model reduction method is presented, which is suitable for networks with large number of ports. By using prior information about the type of the loads that can be connected to the ... 详细信息
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Generating Reduced Order models for High Speed VLSI Interconnects using Balancing-Free Square Root Method
Generating Reduced Order Models for High Speed VLSI Intercon...
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Principles of Advanced and Distributed simulation (PADS), 2006 workshop on;Avignon,France
作者: J. V. R. Ravindra M. B. Srinivas Center for VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad India
This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU t... 详细信息
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