检索结果-内蒙古大学图书馆

IEEE International workshop on Behavioral modeling and simulation (BMAS)

作者： P. Li L.T. Pileggi Department of ECE Carnegie Mellon University Pittsburgh PA USA

We present a technique for modeling nonlinear distortion of multirate time-varying communication circuits. To properly consider the weakly nonlinear distortion effects in circuits with multiple large-signal excitations, we capture the quasiperiodic boundary condition of the system Volterra kernels using a multivariate formulation. We then extend the model order reduction work of P. Li et al. (2003) to reduce this large multivariate representation for compact modeling. The proposed approach is demonstrated on a heterodyne front-end receiver.

关键词： Nonlinear distortion Time varying systems Boundary conditions circuit simulation Time varying circuits Coupling circuits Radio frequency Nonlinear systems Transfer functions Laplace equations

来源：评论

学校读者我要写书评

暂无评论

High-level area/delay/power estimation for low power system VLSIs with gated clocks

引用

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2002年第4期E85A卷 827-834页

作者： Noda, S Togawa, N Yanagisawa, M Ohtsuki, T Waseda Univ Dept Elect Informat & Commun Engn Adv Res Inst Sci & Engn Tokyo 1698555 Japan Univ Kitakyushu Dept Informat & Media Sci Kitakyushu Fukuoka 8080135 Japan

At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating tradeoff between power and area/delay by applying gated clocks is very important. In this paper. we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.

关键词： high-level synthesis power estimation gated clock switching activity sequential circuit

来源：评论

学校读者我要写书评

暂无评论

Second generation delay model for submicron CMOS process

引用

10th International workshop on Integrated circuit Design

作者： Rezzoug, M Maurine, P Auvergne, D Univ Montpellier 2 LIRMM UMR CNRS C5506 F-34392 Montpellier France

ISBN: (纸本)3540410686

The performance characterization and optimization of logic circuits under rapid process migration is one of the big challenges of nowadays submicron CMOS technologies. This characterization must be robust on a wide design space in predicting the performance evolution of designs. In this paper we present a second generation of analytical modeling of delay performance, considering speed carrier desaturation induced non linear variation of delay, I/O coupling, load and input ramp effects. A First model is deduced for inverters and then extended to logic gates through a reduction protocol of the serial transistor array, Validations are given, on a 0.18mum process, by comparing values of simulated (HSPICE) and calculated delay for different configurations of inverters and gates.

关键词： Computer circuits

来源：评论

学校读者我要写书评

暂无评论

Predictive microwave device design by coupled electro-thermal simulation based on a fully physical thermal model

Predictive microwave device design by coupled electro-therma...

引用

IEEE workshop on, High Performance Electron Devices for Microwave and Optoelectronic Applications

作者： T. Batty C.E. Christoffersen S. David A.J. Panks R.G. Johnson C.M. Snowden I.B. Steer Institute of Microwaves and Photonics School of Electronic and Electrical Engineering University of Leeds Leeds UK Department of Electrical and Computer Engineering North Carolina State University Raleigh NC USA

ISBN: (纸本)078036550X

Coupled electro-thermal simulations are performed to demonstrate predictive design of microwave devices. These simulations are based on an original, fully physical, thermal impedance matrix approach, capable of describing 'nearly exactly' time-dependent heat flow in complex 3-dimensional systems, whilst requiring no model reduction for electro-thermal CAD. This thermal model is validated by thermal imaging of passive grid arrays representative of spatial power combining architectures. Electro-thermal transient, single-tone, two-tone and multi-tone harmonic balance simulations are presented for a MESFET amplifier, by implementing the thermal impedance matrix approach in microwave circuit simulator, Transim (NCSU).

关键词： Microwave devices Electromagnetic heating Impedance circuit simulation Predictive models Cogeneration Reduced order systems Design automation Power system modeling Microwave imaging

来源：评论

学校读者我要写书评

暂无评论

Proceedings - IEEE Alessandro Volta Memorial workshop on Low-Power Design, VOLTA 1999

Proceedings - IEEE Alessandro Volta Memorial Workshop on Low...

引用

1999 IEEE Alessandro Volta Memorial workshop on Low-Power Design, VOLTA 1999

ISBN: (纸本)0769500196

The proceedings contain 21 papers. The topics discussed include: power management issues in high performance processor design;are early computer architectures a source of ideas for low-power?;power dissipation in the next generation processors;system-level dynamic power management;trading-off power versus area through a parameterizable model for virtual memory management;power performance advantages of victim buffer in high-performance processors;interaction between sub-word parallelism exploitation and low power code transformations for VLIW Multi-media processors;reduced power dissipation through truncated multiplication;A CMOS power-delay model for CAD optimization tools;total least squares approach for behavioral power modeling;transformation-based peak power reduction for test sequences;low-power low-voltage 4-2 compressors for VLSI applications;RTL power estimation in an industrial design flow;a new short circuit power model for complex CMOS gates;a comparison of stream synthesis methods for fast power simulation;maximum leakage power estimation for CMOS circuits;will VLSI digital circuits exist in GaAs?;pipelined DSP design with a true single-phase energy-recovering logic style;mismatch-shaped pseudo-passive two-capacitor DAC;low power issues in a digital programmable artificial retina;analytical model for high level power modeling of combinational and sequential circuits;and lookup table power macro-models for behavioral library components.

关键词：

来源：评论

学校读者我要写书评

暂无评论

circuit modeling of the effect of temperature on semiconductor lasers

Circuit modeling of the effect of temperature on semiconduct...

引用

Proceedings of the 1997 9th International workshop on the Physics of Semiconductor Devices, IWPSD. Part 1 (of 2)

作者： Madhan, M.Ganesh Gunasekaran, N. Vaya, P.R. Anna Univ Madras India

A circuit modeling approach to study the effect of temperature on the modulation dynamics of DH and QW Lasers is attempted using a simple and less time consuming PSPICE circuit simulator. The circuit model is developed from the `rate equations' for which the temperature dependent parameters are chosen suitably. The DC sweep simulation shows increased threshold current for increase in temperature. At higher temperatures, the pulse response reveals reduction in optical pulse amplitude and an increase in relaxation oscillations. A reduction in frequency chirp amplitude at increased temperature is also observed.

关键词： Quantum well lasers

来源：评论

学校读者我要写书评

暂无评论

modeling and circuit reduction methodology for circuit simulation of DRAM circuits

Modeling and circuit reduction methodology for circuit simul...

引用

Records of the 1995 IEEE International workshop on Memory Technology, Design and Testing

作者： Kao, William H. Gao, Xiao C. Hamazaki, Ryoji Kikuchi, Hidekazu Cadence Design Systems San Jose United States

As DRAM circuit densities increase, and feature size decrease, circuit simulation of these circuits are becoming increasingly more critical and challenging in order to handle the large circuit capacity (millions of transistors) together with the accuracy required to take into account submicron effects. This paper presents a modeling and circuit reduction methodology and a DRAM modeling tool that lets the user configure the model architecture, parameterize and generate reduced macromodels, select and switch different level models, link the different models, and define circuits stimulus signals for the circuit simulation of the entire DRAM design.

关键词： Random access storage

来源：评论

学校读者我要写书评

暂无评论

A modeling and circuit reduction methodology for circuit simulation of DRAM circuits

A modeling and circuit reduction methodology for circuit sim...

引用

IEEE International workshop on Memory Technology, Design and Testing

作者： W.H. Kao X.C. Gao R. Hamazaki H. Kikuchi Cadence Design Systems Inc. San Jose CA USA OKI Electric Industry Company Limited Tokyo Japan

As DRAM circuit densities increase and feature sizes decrease, circuit simulation of these circuits is becoming increasingly more critical and challenging in order to handle the large circuit capacity (millions of transistors), together with the accuracy required to take into account submicron effects. This paper presents a modeling and circuit reduction methodology and a DRAM modeling tool that lets the user configure the model architecture, parameterize and generate reduced macromodels, select and switch between different-level models, link the different models, and define circuit stimulus signals for the circuit simulation of the entire DRAM design.

关键词： circuit simulation Random access memory Switches Wire Switching circuits Power supplies Driver circuits Decoding Rivers Signal generators

来源：评论

学校读者我要写书评

暂无评论

Rational formulation of thermal circuit models by finite element method and model reduction techniques for electro-thermal simulation

Rational formulation of thermal circuit models by finite ele...

引用

Proceedings of the IEEE 4th workshop on Computers in Power Electronics

作者： Hsu, J.T. Vu-Quoc, L. Univ of Florida United States

This paper presents a rational approach to construct thermal circuit networks equivalent to a discretization of the heat equation by the Finite Element Method (FEM). After the derivation of FEM-based thermal circuit networks, model reduction techniques are further applied to derive reduced thermal circuit networks for the efficient electro-thermal simulation of power electronic circuits and devices in the circuit simulators.

关键词： Semiconductor device models

来源：评论

学校读者我要写书评

暂无评论

A rational formulation of thermal circuit models by finite element method and model reduction techniques for electro-thermal simulation

A rational formulation of thermal circuit models by finite e...

引用

IEEE workshop on Computers in Power Electronics

作者： T. Hsu L. Vu-Quoc University of Florida Alford FL USA

This paper presents a rational approach to construct thermal circuit networks equivalent to a discretization of the heat equation by the finite element method (FEM). After the derivation of FEM-based thermal circuit networks, model reduction techniques are further applied to derive reduced thermal circuit networks for the efficient electro-thermal simulation of power electronic circuits and devices in circuit simulators.< >

关键词： Finite element methods Reduced order systems circuit simulation Symmetric matrices Electronic packaging thermal management Power electronics Coupling circuits Finite difference methods Nonlinear equations Computational modeling

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：