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29th International workshop on Thermal Investigations of ICs and Systems,(THERMINIC)

作者： Pohl, Laszlo Budapest Univ Technol & Econ Dept Electron Devices Fac Elect Engn & Informat Muegyetem rkp 3 H-1111 Budapest Hungary

ISBN: (纸本)9798350318623

This paper presents a new open-source simulator that aims to provide a tool to study a wide range of current and future problems requiring high-resolution distributed simulation in engineering practice, especially in microelectronics. The problem to be studied is defined as a circuit model, which can be specified by a SPICE-like description. The simulator solves this circuit using the highly efficient Successive Network reduction Method, optimized specifically for solving circuit models of fields discretized by the Finite Differences or Finite Volumes methods. The circuits can be extended with programmable special components: controllers, to easily implement special tasks such as hysteresis or ray tracing modelling.

关键词： FVM FDM circuit simulation distributed simulation

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Generation of efficient behavioral models using model compilation and model reduction techniques

Generation of efficient behavioral models using model compil...

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10th International workshop on Symbolic and Numerical Methods, modeling and Applications to circuit Design, SM2ACD 2008

作者： Halfmann, Thomas Broz, Jochen Knoth, Christoph Platte, Daniel Rotter, Peter Fraunhofer ITWM System Analysis Prognosis and Control Fraunhofer-Platz 1 Kaiserslautern 67663 Germany Technische Universität München Lehrstuhl für Entwurfsautomatisierung Arcisstr. 21 München 80333 Germany Qimonda AG Am Campeon 1-12 Neubiberg 85579 Germany Infineon Technologies AG Am Campeon 1-12 Neubiberg 85579 Germany

ISBN: (纸本)9783000257612

Symbolic methods are a promising technology for the automatic bottom-up generation of analog behavioral models for an efficient verification in circuit design. However, in comparison to standard circuit simulation these behavioral models show up to now an insufficient simulation performance. This contribution shows how the simulation performance can be decisively improved by using a new combination of symbolic model reduction and an optimized model compilation. The proposed approach is applied to a standard analog circuit component where a real speedup has been achieved comparing the standard netlist-based circuit simulation against the behavioral simulation.

关键词： circuit simulation

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workshop on model reduction for circuit simulation

作者： Stykel, Tatjana

ISBN: (纸本)9789400700888

In recent years, model order reduction has been recognized to be a powerful tool in analysis and simulation of integrated circuits. We consider balancing-related model reduction methods for differential-algebraic equations arising in circuit simulation. We show how positive real and bounded real balanced truncation can be used for passivity-preserving model reduction of circuit equations. These methods are based on balancing the solutions of projected Lur'e or Riccati matrix equations and admit computable error bounds. We also discuss efficient algorithms for solving such matrix equations that exploit the topological structure of circuit equations. Numerical experiments demonstrate the performance of the presented model reduction methods. © 2011 Springer Science+Business Media B.V.

关键词： circuit simulation

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circuit realization method for reduced order inductive PEEC modeling circuits

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COMPEL-THE INTERNATIONAL JOURNAL FOR COMPUTATION AND MATHEMATICS IN ELECTRICAL AND ELECTRONIC ENGINEERING 2016年第3期35卷 1203-1217页

作者： Trung-Son Nguyen Tung Le Duc Son Thanh Tran Guichon, Jean-Michel Chadebec, Olivier G2Elab ENSE3 Grenoble Elect Engn Lab St Martin Dheres France Hanoi Univ Sci & Technol Sch Elect Engn Dept Elect Power Syst Hanoi Vietnam Hanoi Univ Sci & Technol Int Res Inst Computat Sci & Engn ICSE Hanoi Vietnam Elect Power Univ Dept Elect Engn Hanoi Vietnam CNRS G2ELab Grenoble France

Purpose - The purpose of this paper is to synthesize equivalent circuit obtained from reduced order model of large scale inductive PEEC circuits. Design/methodology/approach - This paper describes an original approach for reducing and synthesizing large parasitic RLM electrical circuits coming from inductive Partial Element Equivalent circuit (PEEC) models. The proposed technique enables the re - use of the reduced order model in the time domain circuit simulation context. Findings - The paper shows how to use a synthesis method to realize an equivalent circuit issued from compressed PEEC circuits. Originality/value - The coupling between methods PEEC and a compressed method as Fast Multipole Method in order to reduce time and space consuming are well known. The innovation here is to realize a smaller circuit equivalent with the original large scale PEEC circuits to use in temporal simulation tools. Moreover, this synthesis method reduces time and memories for modelling industrial application while maintaining high accuracy.

关键词： Equivalent circuit synthesis method FMM method Interconnect circuit model order reduction PEEC method SPRIM IOPOR

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modeling and circuit reduction methodology for circuit simulation of DRAM circuits

Modeling and circuit reduction methodology for circuit simul...

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Records of the 1995 IEEE International workshop on Memory Technology, Design and Testing

作者： Kao, William H. Gao, Xiao C. Hamazaki, Ryoji Kikuchi, Hidekazu Cadence Design Systems San Jose United States

As DRAM circuit densities increase, and feature size decrease, circuit simulation of these circuits are becoming increasingly more critical and challenging in order to handle the large circuit capacity (millions of transistors) together with the accuracy required to take into account submicron effects. This paper presents a modeling and circuit reduction methodology and a DRAM modeling tool that lets the user configure the model architecture, parameterize and generate reduced macromodels, select and switch different level models, link the different models, and define circuits stimulus signals for the circuit simulation of the entire DRAM design.

关键词： Random access storage

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Symbolic model order reduction

Symbolic model order reduction

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IEEE International workshop on Behavioral modeling and simulation, BMAS 2003

作者： Hu, B.P. Shi, G. Shi, C.-J.R. Mixed-Signal CAD Research Laboratory Department of Electrical Engineering University of Washington SeattleWA98195 United States

ISBN: (纸本)0780381351

Symbolic model order reduction (SMOR) is the problem of reducing a large circuit that contains symbolic circuit parameters to smaller low order models at its ports. Several methods, including symbol isolation, single frequency point reduction, and multiple frequency point reduction, are described and compared. Test circuits with simulation results are presented to demonstrate the accuracy and efficiency of SMOR. © 2003 IEEE.

关键词： Chromium

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Real-Time Electromagnetic Visualisation for Large 3D Accelerated models 23

Real-Time Electromagnetic Visualisation for Large 3D Acceler...

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IEEE 23rd workshop on Control and modeling for Power Electronics (COMPEL)

作者： Jalal, Bawar Blakaj, Valon Greedy, Steve Evans, Paul Univ Nottingham PEMC Grp Nottingham England Univ Nottingham GGIEMR Grp Nottingham England

ISBN: (纸本)9781665410816

Previous work has shown that real-time electromagnetic models can be used to enable an augmented reality-based visualisation of the magnetic field around a single wire over a ground plane. However, as model complexity is increased, the memory usage and simulation times increase considerably, to the point that it would be impossible to use in a real-time visualisation. In this paper, previous efforts are substantially improved by incorporating the Fast Multipole formulation of the Partial Element Equivalent circuit method alongside the PRIMA model order reduction algorithm. A significantly larger model with 11156 ODEs has been simulated in real-time for smooth augmented reality visualisations. Experimental measurements are used to validate the accuracy of the simulation models used.

关键词： real time model order reduction augmented reality power electronics electromagnetic analysis time domain simulation frequency domain simulation partial element equivalent circuit method

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On synthesis of reduced order models

On synthesis of reduced order models

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workshop on model reduction for circuit simulation

作者： Ionutiu, Roxana Rommes, Joost NXP Semiconductors HTC46-2.08 5656 AE Eindhoven Netherlands

ISBN: (纸本)9789400700888

A framework for model reduction and synthesis is presented, which enables the re-use of reduced order models in circuit simulation. Two synthesis techniques are considered for obtaining the circuit representation (netlist) of the reduced model: (1) by means of realizing the reduced transfer function and (2) by unstamping the reduced system matrices. For both methods, advantages and limitations are discussed. Especially when model reduction exploits structure preservation, we show that using the model as a current-driven element is possible, and allows for synthesis without controlled sources. The presented framework serves as a basis for reduction of large parasitic R/RC/RCL networks. © 2011 Springer Science+Business Media B.V.

关键词： circuit simulation

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model reduction of periodic descriptor systems using balanced truncation

Model reduction of periodic descriptor systems using balance...

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workshop on model reduction for circuit simulation

作者： Benner, Peter Hossain, Mohammad-Sahadet Stykel, Tatjana Fakultät für Mathematik TU Chemnitz 09107 Chemnitz Germany Institut für Mathematik MA 4-5 TU Berlin Straße des 17.Juni 136 10623 Berlin Germany

ISBN: (纸本)9789400700888

Linear periodic descriptor systems represent a broad class of time evolutionary processes in micro-electronics and circuit simulation. In this paper, we consider discrete-time linear periodic descriptor systems and study the concepts of periodic reachability and observability Gramians. We also discuss a lifted representation of periodic descriptor systems and propose a balanced truncation model reduction method for such *** behaviour of the suggested model reduction technique is illustrated using a numerical example. © 2011 Springer Science+Business Media B.V.

关键词： circuit simulation

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Lifetime of CMOS circuits Evaluation by Means of Electro-thermal simulations

Lifetime of CMOS Circuits Evaluation by Means of Electro-the...

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19th International workshop on Thermal Investigations of ICs and Systems (THERMINIC)

作者： Garci, Maroua Kammerer, Jean-Baptiste Hebrard, Luc ICube Strasbourg France

ISBN: (纸本)9781479922710

An electro-thermal compact model of MOSFET which takes the hot carriers effects into account is presented in this paper. This new compact model evaluates the threshold voltage shift as well as the mobility reduction induced by the increase of the density of states at the Si/SiO2 interface produced by hot carriers. This physical effect depends on the biasing conditions and the temperature of the device. Results obtained on a single transistor are presented and compared to experimental results. Electro-thermal simulations at chip level are presented through a circuit dedicated to effective aging evaluation. simulation results clearly show how the temperature reduces the lifetime of circuits. This new electro-thermal compact model coupled to our electro-thermal simulation tool offers the possibility to evaluate the lifetime of analog CMOS circuit.

关键词： mean life chip level single-transistor Hot carriers thermal simulation Electric circuits Complementary Metal Oxide Semiconductor increased density simulation tool Compact Compact Pattern metal-oxide-semiconductor field effect transistors voltage drift Density of states simulating

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