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检索条件"任意字段=Workshop on Model Reduction for Circuit Simulation"
121 条 记 录,以下是41-50 订阅
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A New Approach for the Identification of Reduced Thermal models  20
A New Approach for the Identification of Reduced Thermal Mod...
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20th International workshop on Thermal Investigations of ICs and Systems (THERMINIC)
作者: Blanchard, Jean-Louis Abid, Fatma Chevallier, Gael Valeo F-94046 Creteil France Supmeca Paris Lissma F-93400 St Ouen France
This paper describes a method aimed at producing reduced order models in state-space form for speeding up the transient thermal simulation of mechatronics products. Designed in a non-intrusive framework, this method i... 详细信息
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Time domain analog circuit simulation
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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 2006年 第2期185卷 441-459页
作者: Fijnvandraat, JG Houben, SHMJ ter Maten, EJW Peters, JMF Philips Res Labs Eindhoven Netherlands Eindhoven Univ Technol ED&T AS NL-5656 AA Eindhoven Netherlands Magma Design Automat Eindhoven Netherlands
Recent developments of new methods for simulating electric circuits are described. Emphasis is put on methods that fit existing datastructures for backward differentiation formulae methods. These methods can be modifi... 详细信息
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A general method for multi-port active network reduction and realization
A general method for multi-port active network reduction and...
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BMAS 2005 - 2005 IEEE International Behavioral modeling and simulation workshop
作者: Liu, Pu Qi, Zhenyu Aviles, Amalia Tan, Sheldon X.-D. Department of Electrical Engineering University of California Riverside CA 92521 United States
This paper presents a novel compact modeling technique for linear(ized) active analog circuits. The new method is based on a recently proposed general s-domain hierarchical modeling and analysis method. In this work, ... 详细信息
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Structure preserving port-Hamiltonian model reduction of electrical circuits
Structure preserving port-Hamiltonian model reduction of ele...
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workshop on model reduction for circuit simulation
作者: Polyuga, Rostylav V. Van Der Schaft, Arjan J. Johann Bernoulli Institute for Mathematics and Computer Science University of Groningen P.O. Box 407 9700 AK Groningen Netherlands
This paper discusses model reduction of electrical circuits based on a port-Hamiltonian representation. It is shown that by the use of the Kalman decomposition an uncontrollable and/or unobservable port-Hamiltonian sy... 详细信息
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Fast and Robust Symbolic model Order reduction with ANALOG INSYDES
Fast and Robust Symbolic Model Order Reduction with ANALOG I...
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13th International workshop on Computer Algebra in Scientific Computing
作者: Hauser, Matthias Salzig, Christian Dreyer, Alexander Fraunhofer Inst Ind Math ITWM D-67663 Kaiserslautern Germany
Nowadays analog circuits become more and more complex. The growing number of devices hinder to understand the full behavior of these and new methods are required to support the design. This paper presents two new meth... 详细信息
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BMAS 2006 - Proceedings of the 2006 IEEE International Behavioral modeling and simulation workshop
BMAS 2006 - Proceedings of the 2006 IEEE International Behav...
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2006 IEEE International Behavioral modeling and simulation workshop, BMAS 2006
The proceedings contain 26 papers. The topics discussed include: variational compact modeling and simulation for linear dynamic systems;statistical gate level simulation via voltage controlled current source models;be... 详细信息
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Recycling Krylov subspaces for solving linear systems with successively changing right-hand sides arising in model reduction
Recycling Krylov subspaces for solving linear systems with s...
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workshop on model reduction for circuit simulation
作者: Benner, Peter Feng, Lihong Mathematik in Industrie und Technik Fakultät für Mathematik Technische Universität Chemnitz Reichenhainer Str. 41 01926 Chemnitz Germany
We discuss the numerical solution of successive linear systems of equations , by iterative methods based on recycling Krylov subspaces. We propose various recycling algorithms which are based on the generalized conjug... 详细信息
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Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
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18th International workshop on Power and Timing modeling, Optimization and simulation (PATMOS)
作者: Machado, Felipe Riesgo, Teresa Torroja, Yago Univ Rey Juan Carlos ESCET Dept Tecnol Elect C Tulipan S-N Madrid 28933 Spain Univ Politecn Madrid Ctr Elec Ind ETSII Madrid 28066 Spain
This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires larg... 详细信息
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Analysis of current and voltage distribution in the first Japanese qualification sample of an ITER TF conductor
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CRYOGENICS 2010年 第3期50卷 129-138页
作者: Koizumi, Norikiyo Matsui, Kunihiro Okuno, Kiyoshi Japan Atom Energy Agcy ITER Superconducting Magnet Dev Grp Naka Ibaraki 3110193 Japan
The critical currents of the Japanese ITER TF conductors made through an internal-tin and bronze process were preliminarily estimated to be about 5 7 K. which approximates the design value of 5.7K, and about 6 1 K, re... 详细信息
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Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry
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16th International workshop on Power and Timing modeling, Optimization and simulation
作者: Palma, Jose C. S. Indrusiak, Leandro Soares Moraes, Fernando G. Ortiz, Alberto Garcia Glesner, Manfred Reis, Ricardo A. L. UFRGS PPGC II BR-9500 Porto Alegre RS Brazil TU Darmstadt MES D-64283 Darmstadt Germany PUCRES FACIN PPGCC Porto Alegre RS Brazil
This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed wit... 详细信息
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