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20th International workshop on Thermal Investigations of ICs and Systems (THERMINIC)

作者： Blanchard, Jean-Louis Abid, Fatma Chevallier, Gael Valeo F-94046 Creteil France Supmeca Paris Lissma F-93400 St Ouen France

ISBN: (纸本)9781479954155

This paper describes a method aimed at producing reduced order models in state-space form for speeding up the transient thermal simulation of mechatronics products. Designed in a non-intrusive framework, this method is implemented as an offline tool that post-processes the inputs and outputs of a detailed reference model considered as a black box. The reduction algorithm is based on robust linear algebra tools, such as the householder decomposition and the least square approximation. Thanks to the underlying modal representation, the model order, typically equal to the number of observation points, can be also further reduced. A first linear test case illustrates the quality of the results. The investigation of various input signals ensuring the reliability of the identification process while minimizing the simulation time of the detailed model, as well as the derivation of non-linear reduced models, are the ongoing paths of improvement and extension.

关键词： least squares approximations linear algebra thermal conductivity householder decomposition identification process least square approximation linear algebra tools reduced order models reduced thermal models reliability Computational modeling Conferences Data models Heating Integrated circuit modeling Mathematical model Vectors

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Time domain analog circuit simulation

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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 2006年第2期185卷 441-459页

作者： Fijnvandraat, JG Houben, SHMJ ter Maten, EJW Peters, JMF Philips Res Labs Eindhoven Netherlands Eindhoven Univ Technol ED&T AS NL-5656 AA Eindhoven Netherlands Magma Design Automat Eindhoven Netherlands

Recent developments of new methods for simulating electric circuits are described. Emphasis is put on methods that fit existing datastructures for backward differentiation formulae methods. These methods can be modified to apply to hierarchically organized datastructures, which allows for efficient simulation of large designs of circuits in the electronics industry. (c) 2005 Elsevier B.V. All rights reserved.

关键词： transient analysis modified nodal analysis differential-algebraic equations hierarchical datastructures recursion BDF Radau Rosenbrock-Wanner MEBDF parallelism model reduction table modeling multi-rate multi-tone mixed-signal mixed-level

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A general method for multi-port active network reduction and realization

A general method for multi-port active network reduction and...

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BMAS 2005 - 2005 IEEE International Behavioral modeling and simulation workshop

作者： Liu, Pu Qi, Zhenyu Aviles, Amalia Tan, Sheldon X.-D. Department of Electrical Engineering University of California Riverside CA 92521 United States

ISBN: (纸本)078039352X

This paper presents a novel compact modeling technique for linear(ized) active analog circuits. The new method is based on a recently proposed general s-domain hierarchical modeling and analysis method. In this work, based on the characteristics of analog circuits, we propose a constrained linear least square based method to optimize the order reduced admittance matrices with respect to both magnitude and phase responses up to the given frequency range. Theoretically we show that the hierarchical reduction does not change the reciprocity property of the linear circuit. For analog active circuits, which typically are non-reciprocal, so do the orderreduced circuit admittance matrices after hierarchical reduction. We propose a novel general multi-port, non-reciprocal network realization method. The resulting modeling algorithm can take in the SPICE netlists of active circuits and generate high-fidelity compact macro models of the active circuits with easily controlled model accuracy and complexity. The experimental results on two low-pass active filters demonstrate effectiveness of the proposed algorithm. © 2005 IEEE.

关键词： Analog computers

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Structure preserving port-Hamiltonian model reduction of electrical circuits

Structure preserving port-Hamiltonian model reduction of ele...

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workshop on model reduction for circuit simulation

作者： Polyuga, Rostylav V. Van Der Schaft, Arjan J. Johann Bernoulli Institute for Mathematics and Computer Science University of Groningen P.O. Box 407 9700 AK Groningen Netherlands

ISBN: (纸本)9789400700888

This paper discusses model reduction of electrical circuits based on a port-Hamiltonian representation. It is shown that by the use of the Kalman decomposition an uncontrollable and/or unobservable port-Hamiltonian system is reduced to a controllable/observable system that inherits the port-Hamiltonian structure. Energy and co-energy variable representations for port-Hamiltonian systems are defined and the reduction procedures are used for both representations. These exact reduction procedures motivate two approximate reduction procedures that are structure preserving for general port-Hamiltonian systems, one reduction procedure is called the effort-constraint reduction methods. The other procedure is structure preserving under a given condition. A numerical example illustrating the model reduction of a ladder network as a port-Hamiltonian system is considered. © 2011 Springer Science+Business Media B.V.

关键词： Timing circuits

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Fast and Robust Symbolic model Order reduction with ANALOG INSYDES

Fast and Robust Symbolic Model Order Reduction with ANALOG I...

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13th International workshop on Computer Algebra in Scientific Computing

作者： Hauser, Matthias Salzig, Christian Dreyer, Alexander Fraunhofer Inst Ind Math ITWM D-67663 Kaiserslautern Germany

ISBN: (纸本)9783642235672

Nowadays analog circuits become more and more complex. The growing number of devices hinder to understand the full behavior of these and new methods are required to support the design. This paper presents two new methods for handling complex nonlinear analog circuits which are available in the new release ANALOG INSYDES 2011, the MATHEMATICA toolbox for symbolic modeling, analysis and reduction of analog circuits. The transient;symbolic model order reduction allows the approximation of behavioral models keeping static and dynamic properties. The new solving algorithm for symbolic equation systems based on sequential equations accelerates the simulation of the reference system as well as the verification of the reduced models. Furthermore, it increases the robustness of the solver permitting analyzes of significantly larger symbolic systems. As example, a voltage controller circuit is reduced using the introduced methods.

关键词： Analog circuits

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BMAS 2006 - Proceedings of the 2006 IEEE International Behavioral modeling and simulation workshop

BMAS 2006 - Proceedings of the 2006 IEEE International Behav...

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2006 IEEE International Behavioral modeling and simulation workshop, BMAS 2006

ISBN: (纸本)0780397428

The proceedings contain 26 papers. The topics discussed include: variational compact modeling and simulation for linear dynamic systems;statistical gate level simulation via voltage controlled current source models;behavioral-level performance modeling of analog and mixed-signal systems using support vector machines;mixed modeling of SAW delay line using VHDL;macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design;an extended SVD-based terminal and model order reduction algorithm;a referenced geometry based configuration scalable Mextram model for bipolar transistors;modeling of spring constant and pull-down voltage of non-uniform RF MEMS cantilever;SCISIP-program for switched circuit analysis in Matlab;event-driven modeling and simulation of a digital PLL;simulation of power grid networks considering wires and lognormal leakage current variations;and SPICE modeling of free-space optical systems.

关键词： Linear systems

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Recycling Krylov subspaces for solving linear systems with successively changing right-hand sides arising in model reduction

Recycling Krylov subspaces for solving linear systems with s...

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workshop on model reduction for circuit simulation

作者： Benner, Peter Feng, Lihong Mathematik in Industrie und Technik Fakultät für Mathematik Technische Universität Chemnitz Reichenhainer Str. 41 01926 Chemnitz Germany

ISBN: (纸本)9789400700888

We discuss the numerical solution of successive linear systems of equations , by iterative methods based on recycling Krylov subspaces. We propose various recycling algorithms which are based on the generalized conjugate residual (GCR) method. The recycling algorithms reuse the descent vectors computed while solving the previous linear systems , such that a lot of computational work can be saved when solving the current system Ax = b i . The proposed algorithms are robust for solving sequences of linear systems arising in circuit simulation. Sequences of linear systems need to be solved, e.g., in model order reduction (MOR) for systems with many terminals. Numerical experiments illustrate the efficiency and robustness of the proposed method. © 2011 Springer Science+Business Media B.V.

关键词： Linear systems

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Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

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18th International workshop on Power and Timing modeling, Optimization and simulation (PATMOS)

作者： Machado, Felipe Riesgo, Teresa Torroja, Yago Univ Rey Juan Carlos ESCET Dept Tecnol Elect C Tulipan S-N Madrid 28933 Spain Univ Politecn Madrid Ctr Elec Ind ETSII Madrid 28066 Spain

ISBN: (纸本)9783540959472

This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits;therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits;whilst error seems to decrease with the circuit size.

关键词： Switching activity CAD RTL BDD activity estimation digital circuit design VHDL circuit partition power estimation

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Analysis of current and voltage distribution in the first Japanese qualification sample of an ITER TF conductor

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CRYOGENICS 2010年第3期50卷 129-138页

作者： Koizumi, Norikiyo Matsui, Kunihiro Okuno, Kiyoshi Japan Atom Energy Agcy ITER Superconducting Magnet Dev Grp Naka Ibaraki 3110193 Japan

The critical currents of the Japanese ITER TF conductors made through an internal-tin and bronze process were preliminarily estimated to be about 5 7 K. which approximates the design value of 5.7K, and about 6 1 K, respectively. at 68 kA and 11 8 T using a short conductor sample To investigate the influence of the current distribution in the sample conductor, a simulation was performed using a lumped circuit model of a cable and static electrical field model for Jackets The simulation results show that a large, non-uniform current distribution is established due to magneto-resistance of the copper in the Joint and an imbalance of contact resistance of the strands to the copper and by poor soldering between the copper shoes, results which make a precise evaluation of the critical current performance difficult. The analytical results indicate that the current sharing temperature of the internal-tin and bronze process conductors is expected to be 6 0 K and 6 7 K. respectively, when the current distribution is uniform In addition, solder filling of the Joints makes the current distribution uniform due to the normal resistance in the high field zone, and the current sharing temperature can be estimated as almost the same as when the current distribution is uniform The other possible solution is to use a thin copper plate with a low RRR to reduce the influence of magneto-resistance and any non-uniformity in contact resistance Conductor performance is under-estimated in this case because the non-uniform current distribution still remains However, the reduction in the estimated current sharing temperature is expected to be a few hundred milli-Kelvins, which seems acceptable as a margin in a qualification trial. (C) 2009 Elsevier Ltd All rights reserved

关键词： Analytical model Current imbalance Cable-in-conduit ITER

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Adaptive coding in Networks-on-Chip: Transition activity reduction versus power overhead of the codec circuitry

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16th International workshop on Power and Timing modeling, Optimization and simulation

作者： Palma, Jose C. S. Indrusiak, Leandro Soares Moraes, Fernando G. Ortiz, Alberto Garcia Glesner, Manfred Reis, Ricardo A. L. UFRGS PPGC II BR-9500 Porto Alegre RS Brazil TU Darmstadt MES D-64283 Darmstadt Germany PUCRES FACIN PPGCC Porto Alegre RS Brazil

ISBN: (纸本)3540390944

This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

关键词： Microprocessor chips

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