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检索条件"任意字段=Workshop on Model Reduction for Circuit Simulation"

共 121 条记录，以下是61-70 订阅

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Characterization and compensation of nonlinearities in a continuous-time first-order ΣΔ ADC

Characterization and compensation of nonlinearities in a con...

引用

IEEE MTT-S International Microwave workshop Series (IMWS)

作者： C. Schmidt J. E. Cousseau J. L. Figueroa R. Wichman S. Werner Instituto de Investigaciones en Ingeniería Eléctrica UNS-CONICET Bahia Blanca Argentina Department of Signal Processing and Acoustics Aalto University School of Science and Engineering Aalto Finland

ISBN: (纸本)9781424457519;9781424457533

We present an approach for compensating nonlinearities in a continuous-time (CT) first-order sigma-delta converter (SDC) with one bit quantization. A reduction of an order of magnitude is obtained in the measured squared error when compared to the uncompensated SDC. Our results confirm a significant improvement in Signal to Noise and Distortion Ratio (SINAD) for single tone input signals and in Spurius Free Dynamic Range (SFDR) for multi-tone inputs.

关键词： Delta-sigma modulation Nonlinear distortion Polynomials Mathematical model circuit simulation Signal processing Quantization Dynamic range Latches Table lookup

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Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level

引用

18th International workshop on Power and Timing modeling, Optimization and simulation (PATMOS)

作者： Machado, Felipe Riesgo, Teresa Torroja, Yago Univ Rey Juan Carlos ESCET Dept Tecnol Elect C Tulipan S-N Madrid 28933 Spain Univ Politecn Madrid Ctr Elec Ind ETSII Madrid 28066 Spain

ISBN: (纸本)9783540959472

This paper presents a partition method for probabilistic switching activity estimation of combinational circuits described at register transfer level (RTL). Probabilistic estimation of switching activity requires large and complex models that could be unfeasible for large circuits;therefore, circuit partitioning becomes a necessary step to address the analysis. Nevertheless, partition methods imply approximations that produce inaccurate results. We present a partition method based on disjoint signals that minimizes the error and, in addition, it is easy to carry out. Results show important reductions on the binary decision diagrams (BDD) of the probabilistic model as well as low errors. Furthermore, the BDD reduction ratio shows a tendency to increase with large circuits;whilst error seems to decrease with the circuit size.

关键词： Switching activity CAD RTL BDD activity estimation digital circuit design VHDL circuit partition power estimation

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A HW/SW Co-design Methodology: An Accurate Power Efficiency model and Design Metrics for Embedded System

A HW/SW Co-design Methodology: An Accurate Power Efficiency ...

引用

3rd International workshop on e-Activity (IWEA2009)/10th ACIS International Conference on Software Engineering Artificial Intelligence, Networking and Parallel/Distributed Computing

作者： Iftikhar, Khan Jeong, Taikyeong Ted Park, Gyungleen Ambler, Anthony P. Myongji Univ Dept Commun Eng Seoul South Korea Jeju Natl Univ Dept Comp Stat Jeju-do South Korea Univ Texas Austin Dept Elect & Comp Eng Austin TX 78712 USA

ISBN: (纸本)9780769536422

Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embedded system design. The aim of this paper is to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to show the system-level partitioning and design. In order to verify the design effectiveness of hardware/software co-design synthesis, we consider the digital power dissipation methodology and its power reduction techniques. To maximize the performance of system, we developed hierarchical design technique and co-design synthesis for power efficient HW/SW co-design process. In the end, we provided simulation results for single circuit with new design vs. circuit integration with hierarchical power efficiency system (HPES), multiple circuits with new design vs. circuit integration with HPES, new design and no load vs. circuit integration with HPES, new design with load vs. circuit integration with HPES.

关键词： Embedded systems hardware/software codesign low-power power metrics

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Generation of efficient behavioral models using model compilation and model reduction techniques

Generation of efficient behavioral models using model compil...

引用

10th International workshop on Symbolic and Numerical Methods, modeling and Applications to circuit Design, SM2ACD 2008

作者： Halfmann, Thomas Broz, Jochen Knoth, Christoph Platte, Daniel Rotter, Peter Fraunhofer ITWM System Analysis Prognosis and Control Fraunhofer-Platz 1 Kaiserslautern 67663 Germany Technische Universität München Lehrstuhl für Entwurfsautomatisierung Arcisstr. 21 München 80333 Germany Qimonda AG Am Campeon 1-12 Neubiberg 85579 Germany Infineon Technologies AG Am Campeon 1-12 Neubiberg 85579 Germany

ISBN: (纸本)9783000257612

Symbolic methods are a promising technology for the automatic bottom-up generation of analog behavioral models for an efficient verification in circuit design. However, in comparison to standard circuit simulation these behavioral models show up to now an insufficient simulation performance. This contribution shows how the simulation performance can be decisively improved by using a new combination of symbolic model reduction and an optimized model compilation. The proposed approach is applied to a standard analog circuit component where a real speedup has been achieved comparing the standard netlist-based circuit simulation against the behavioral simulation.

关键词： circuit simulation

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Scalable symbolic model order reduction

Scalable symbolic model order reduction

引用

2008 IEEE International Behavioral modeling and simulation workshop, BMAS 2008

作者： Shi, Yiyu Het, Lei Shi, C.-J. Richard Electpcal Engineering Dept. UCLA Los AngelesCA 90024 United States Electrical Engineering Dept. UW SeattleWA 98105 United States

ISBN: (纸本)9781424428960

Symbolic model order reduction (SMOR) is to reduce the complexity of a model with symbolic parameters. It is an important problem in analog circuit synthesis and digital circuit modeling with process variations. However, existing symbolic model order reduction (SMOR) methods do not scale well with the number of symbols or with the model order. This paper presents a scalable SMOR algorithm name ly S2 MOR. We first separate the original multi-port multi-symbol system into a set of single-port systems by superposition theorem, and then integrate them together to form a lower-bordered block diagonal (LBBD) structured system. Each block is reduced independently, with a stochastic programming to distribute the given overall model order between blocks for best accuracy. The entire system is efficiently solved by low-rank update. Compared with existing SMOR algorithms, given the same memory space, S2MOR improves accuracy by up to 78% at a similar reduction time. In addition, the factorization and simulation of the reduced model by S2MOR is up to 17 xfaster. © 2008 IEEE.

关键词： Stochastic programming

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Scalable Symbolic model Order reduction

Scalable Symbolic Model Order Reduction

引用

IEEE International workshop on Behavioral modeling and simulation (BMAS)

作者： Yiyu Shi Lei He C.-J. Richard Shi Electrical Engineering Department UCLA Los Angeles CA USA Electrical Engineering Department University of Wisconsin Seattle WA USA

Symbolic model order reduction (SMOR) is to reduce the complexity of a model with symbolic parameters. It is an important problem in analog circuit synthesis and digital circuit modeling with process variations. However, existing symbolic model order reduction (SMOR) methods do not scale well with the number of symbols or with the model order. This paper presents a scalable SMOR algorithm, namely S 2 MOR. We first separate the original multz-port multz-symbol system into a set of single-port systems by superposition theorem, and then integrate them together to form a lower-bordered block diagonal (LBBD) structured system. Each block is reduced independently, with a stochastic programming to distribute the given overall model order between blocks for best accuracy. The entire system is efficiently solved by low-rank update. Compared with existing SMOR algorithms, given the same memory space, S 2 MOR improves accuracy by up to 78% at a similar reduction time. In addition, the factorization and simulation of the reduced model by S 2 MOR is up to 17 times faster.

关键词： circuit simulation Stochastic processes Polynomials Analytical models Large-scale systems Nonlinear circuits Tellurium

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Crosstalk Noise reduction Techniques Using SOI Substrate

Crosstalk Noise Reduction Techniques Using SOI Substrate

引用

Principles of Advanced and Distributed simulation (PADS), 2006 workshop on;Avignon,France

作者： Fargol Hasani Nasser Masoumi Behjat Forouzandeh School of ECE VLSI Research Laboratory University of Tehran Iran

As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques using Silicon On Insulator (SOI) substrate. Coupling through common silicon substrate has become an important limiting factor in high performance ICs. A study of the advantages of using SOI substrate in contrast to bulk is presented in this paper. Through MATLAB software, a system of three coupled wires is modeled as RC distributed networks. A resistive model is used to model both SOI and bulk substrates. The results are compared to the bulk in order to show the advantages of using SOI substrate to reduce crosstalk noise in deep sub micron technology.

关键词： Crosstalk Silicon on insulator technology Mathematical model Frequency Integrated circuit interconnections System performance Integrated circuit reliability Coupling circuits MATLAB Software systems

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Generating Reduced Order models for High Speed VLSI Interconnects using Balancing-Free Square Root Method

Generating Reduced Order Models for High Speed VLSI Intercon...

引用

Principles of Advanced and Distributed simulation (PADS), 2006 workshop on;Avignon,France

作者： J. V. R. Ravindra M. B. Srinivas Center for VLSI and Embedded System Technologies International Institute of Information Technology Hyderabad India

This paper presents a model order reduction technique based on balancing-free square root (BSR) method for high speed coupled integrated circuit interconnects. The salient features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the availability of provable weighted error bounds for the reduced-order system. This paper shows that the balancing-free square root method produces reduced systems that accurately follow the time- and frequency- domain responses of the original system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed BSR achieves more accuracy with less CPU time than the other model order reduction techniques existing in literature.

关键词： Reduced order systems Very large scale integration Integrated circuit interconnections RLC circuits Integrated circuit modeling Central Processing Unit Frequency Transfer functions Capacitance Transmission line matrix methods

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Evaluation of driving performance of piezoelectric actuator with current pulse

Evaluation of driving performance of piezoelectric actuator ...

引用

International workshop on Advanced Motion Control (AMC)

作者： Katsushi Furutani Atsushi Furuta Toyota Technological Institute Nagoya Japan Nano Control Company Limited Shinagawa Tokyo Japan

The authors have proposed a driving method of a piezoelectric actuator by a series of current pulses for the high resolution and the hysteresis reduction. It was compared with the voltage pulse and current linear drives by simulations with Martin's piezoelectric model. In the case of driving at a high pulse rate, no difference was observed among them. The low output impedance of the voltage source causes the ripple of the terminal voltage of the piezoelectric actuator so that the vibration of the actuator sometimes remains. In contrast, no ripple due to the low pulse density was observed in the current pulse drive. Therefore, the current pulse drive is good for the precision positioning.

关键词： Piezoelectric actuators Pulse width modulation Hysteresis Voltage control Pulse circuits Space vector pulse width modulation circuit simulation Signal resolution Displacement control Control systems

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A case study of design improvement based on EMI simulation

A case study of design improvement based on EMI simulation

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5th International Conference and workshop on Compatibility in Power Electronics

作者： Le Bunetel, Jean Charles Gonzalez, David Arias, Antoni Gago, Javier Univ Tours Lab Microelect Power Tours France Univ Politecn Cataluna Dept Elect Engn E-08222 Terrassa Spain

ISBN: (纸本)9781424410545

In this paper we present how the design of a power converter can be effectively improved by means of EMI phenomena simulation. We will consider the design of a converter intended as battery charger for telecommunication facilities. First of all, the electric phenomena involved in the generation of electromagnetic interference are reminded. Then the main ideas used to obtain the EMI simulation model are outlined. A model of the power converter in the frequency-domain is obtained and validated through experimental measurements. Finally, this model is used to improve the design of the converter from the EMI point of view, resulting in a reduction of space, weight and cost of the filtering devices.

关键词： circuit modeling circuit simulation electromagnetic compatibility electromagnetic interference power filters

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