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检索条件"任意字段=Workshop on Model Reduction for Circuit Simulation"

共 121 条记录，以下是81-90 订阅

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Proceedings of the 2003 IEEE International workshop on Behavioral modeling and simulation (IEEE Cat. No.03TH8712)

Proceedings of the 2003 IEEE International Workshop on Behav...

引用

IEEE International workshop on Behavioral modeling and simulation (BMAS)

The following topics are dealt with: modeling languages; automatic model extraction; data modeling; mixed-technology modeling; model reduction; micromechanical device modeling; behavioral modeling; analog simulation; HDL; hardware description languages; AHDL; Verilog-A analog hardware description language; circuit simulation; SPICE simulator; Volterra series; compact modeling.

关键词： SPICE Hardware design languages Microelectromechanical devices

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simulation of multiconductor transmission lines using block-latency insertion method and model order reduction technique

Simulation of multiconductor transmission lines using block-...

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workshop on Electromagnetic Compatibility of Integrated circuits (EMC Compo)

作者： Tadatoshi Sekine Hideki Asai Department of Information Science and Technology Graduate School of Science and Technology Shizuoka University Hamamatsu Japan

This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a model order reduction (MOR) technique. The block-LIM is one of the efficient transient analysis methods adopting an explicit leapfrog finite difference method. In the block-LIM, due to duality of voltage and current variables, they are successfully separated from each other by using a staggered time step placement. Thus, each of them can be updated individually within a local block through a time stepping procedure. In this work, we build a reduced order model of the partitioned local block to improve the efficiency of the block-LIM. Compared to other circuit partitioning techniques coupled with the MOR, the order-reduced block-LIM can easily decrease whole computational costs of the transient simulation. Numerical results show that our approach is adequate for the fast simulation of tightly coupled multiconductor transmission lines with CMOS inverters.

关键词： Integrated circuit modeling Topology RLC circuits Integrated circuit interconnections Transient analysis Electromagnetic compatibility Mathematical model

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Variational Compact modeling and simulation for Linear Dynamic Systems

Variational Compact Modeling and Simulation for Linear Dynam...

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IEEE International workshop on Behavioral modeling and simulation (BMAS)

作者： Jeffrey Fan Ning Mi Sheldon X.-d. Tan Department of Electrical Engineering University of California Riverside CA USA

In this paper, we propose a new statistical model order reduction technique called SSMOR method, that is suitable for considering both intra-die and inter-die process variations. The SSMOR generates order reduced variational models from the original variational circuits. The reduced model can be used for fast statistical performance analysis of interconnect circuits with variational power sources. The SSMOR uses statistical spectrum method to compute the variational moments and Monte Carlo sampling method via modified Krylov subspace reduction method to generate the variational reduced models. Experimental results show that explicit moment matching is not suitable for variational analysis and Krylov subspace projection method is more reliable. The proposed method can deliver about 100times speedup over the pure Monte Carlo based projection-based reduction method with less than 1 % of errors for both means and variances in statistical transient analysis

关键词： RLC circuits Integrated circuit interconnections Monte Carlo methods Computational modeling circuit simulation Polynomials Arithmetic Space technology Costs circuit optimization

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PEEC methods in 2D signal line modeling for mid-frequency on-chip power supply noise simulations

PEEC methods in 2D signal line modeling for mid-frequency on...

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IEEE workshop on Signal Propagation on Interconnects (SPI)

作者： J. Rauscher H.-J. Pfleiderer Department of Microelectronics University of Ulm (EBS) Ulm Germany

In this paper a 2D signal line model is used to simulate the power distribution network (PDN). The proposed method uses an admittance function to model the frequency-dependent resistance and inductance in each direction. This admittance function can be gained directly by model order reduction from a partial element equivalent circuit (PEEC) model. Hence, it is possible to efficiently calculate the model parameters even for irregular PDNs. A fast transient simulation algorithm closely related to the finite-difference time-domain (FDTD) schemes is presented. The alternating-direction-implicit (ADI) method relaxes the time step for the simulation, because it is not limited by a stability criterion.

关键词： Power supplies circuit simulation Admittance Finite difference methods Time domain analysis Power systems Frequency Inductance Equivalent circuits circuit stability

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Provably passive second order model order reduction for package parasitics using spectral zeros

Provably passive second order model order reduction for pack...

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Annual IEEE Northeast workshop on circuits and Systems (NEWCAS)

作者： Mehboob Alam Arthur Nieuwoudt Yehia Massoud Rice Automated Nanoscale Design Group ECE Department Rice University Houston TX USA

In this paper, we developed an accurate and provably passive second order method for the model order reduction of passive circuit models in high performance integrated circuits. The method dynamically selects interpolation points from the system's spectral zeros and provides an automated means to simultaneously guarantee stability and passivity while generating low order models that are accurate across a specified range of frequencies. The results demonstrate that our approach provides more accurate reduced order models than second-order Krylov subspace methods.

关键词： Inductance Integrated circuit modeling Frequency Interpolation circuit simulation Integrated circuit interconnections Conductors Integrated circuit packaging Crosstalk Bonding

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Lifetime of CMOS circuits evaluation by means of electro-thermal simulations

Lifetime of CMOS circuits evaluation by means of electro-the...

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International workshop on Thermal Investigation of ICs and Systems (THERMINIC)

作者： Maroua Garci Jean-Baptiste Kammerer Luc Hebrard ICube Strasbourg France

An electro-thermal compact model of MOSFET which takes the hot carriers effects into account is presented in this paper. This new compact model evaluates the threshold voltage shift as well as the mobility reduction induced by the increase of the density of states at the Si/SiO 2 interface produced by hot carriers. This physical effect depends on the biasing conditions and the temperature of the device. Results obtained on a single transistor are presented and compared to experimental results. Electro-thermal simulations at chip level are presented through a circuit dedicated to effective aging evaluation. simulation results clearly show how the temperature reduces the lifetime of circuits. This new electro-thermal compact model coupled to our electro-thermal simulation tool offers the possibility to evaluate the lifetime of analog CMOS circuit.

关键词： Semiconductor device modeling Aging Temperature sensors Integrated circuit modeling Hot carriers Transistors Mathematical model

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Passivity-preserving parameterized model order reduction for PEEC based full wave analysis

Passivity-preserving parameterized model order reduction for...

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IEEE workshop on Signal Propagation on Interconnects (SPI)

作者： F. Ferranti G. Antonini T. Dhaene L. Knockaert Department of Information Technology IBBT Ghent University Ghent Belgium UAq EMC Laboratory Dipartimento di Ingegneria Elettrica e dellInformazione Università degli Studi dell'' Aquila L'Aquila Italy

ISBN: (纸本)9781424476114;9781424476107

We present a novel parameterized model order reduction technique applicable to the Partial Element Equivalent circuit method that is able to generate parametric reduced order models, stable and passive by construction, over a user defined design space. Overall stability and passivity of the parametric reduced order model are guaranteed by an efficient and reliable combination of traditional passivity-preserving model order reduction methods and interpolation schemes based on a class of positive interpolation operators. A pertinent numerical example validates the proposed parameterized model order reduction approach.

关键词： Reduced order systems Interpolation Computational modeling Equivalent circuits circuit simulation RLC circuits Integral equations Frequency Maxwell equations Conductors

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Switched model of control circuits for DC-DC switching converters: application to integrated circuits UC1525 and UC1846

Switched model of control circuits for DC-DC switching conve...

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IEEE workshop on Computers in Power Electronics

作者： A. Lago C.M. Penalver J. Cea Departmento Tecnología Electrónica Universidad de Vigo Vigo Spain

Two modelling techniques for power convertor circuits are most commonly used today: the average model, which is very conventional, where voltages and/or currents are applied continuously in a scaling form; and the switched model, where voltages and/or currents are applied for a short fraction of the commutation period. In this paper, the switched model technique and the simulation of PWM control circuits for switched mode DC/DC power converters are described. This model has been developed using Intusoft ISSPICE/286 software, which is based on SPICE2G.6 from the University of Berkeley. SPICE simulation is a halfway step between theoretical circuit design and its practical implementation and allows the reduction of design time and the observation and correction of some unwanted or unpredictable features of the theoretical design. The modelling and simulation techniques are applied to the popular PWM control integrated circuits UC1525 and UC1846. Several parts, which are simulated together with subcircuit lists, including the oscillator, the error amplifier and the comparator, are described. Finally, the efficacy of this model is verified.< >

关键词： Switching circuits Switching converters circuit simulation Pulse width modulation Voltage Integrated circuit modeling Pulse width modulation converters SPICE circuit synthesis Oscillators

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An Extended SVD-based Terminal and model Order reduction Algorithm

An Extended SVD-based Terminal and Model Order Reduction Alg...

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IEEE International workshop on Behavioral modeling and simulation (BMAS)

作者： Pu Liu Sheldon X.-d. Tan Boyuan Yan Bruce McGaughy Department of Electrical Engineering University of California Riverside CA USA Cadence Design Systems Inc. San Jose CA USA

The paper proposes a new combined terminal and model order reduction method for compact modeling of interconnect circuits. The new method extends the existing SVDMOR method by using higher order moment information for terminal responses during the terminal reduction and by applying separate SVD low-rank approximations on input and output terminals respectively. This is in contrast to SVDMOR method where input and output terminal responses are SVD approximated at the same time, which can lead to large error when the numbers of inputs and outputs are quite different. We analyze the passivity requirement for combined terminal and model order reduction and show the passivity enforcement may significantly hamper the terminal reduction effects. We also improve the computation efficiency of SVDMOR. Our experimental results show that ESVDMOR outperforms the SVDMOR in terms of accuracy for the similar reduced model sizes in a number of interconnect circuits when the input and output terminals are different

关键词： RLC circuits Timing Integrated circuit interconnections Complexity theory Degradation Transfer functions Clocks Reduced order systems

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Symbolic simulation as a simplifying strategy for SoC verification

Symbolic simulation as a simplifying strategy for SoC verifi...

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IEEE International workshop on System-on-Chip for Real-Time Applications

作者： E. Dumitrescu D. Borrione TIMA Laboratory Grenoble France

The successful application of model-checking to industrial designs requires methods for reducing the complexity of the model. This paper presents an original strategy, for a well identified class of circuit behaviors; by running an appropriate symbolic simulation pattern before the actual proof of a temporal formula, an important FSM model simplification can be obtained. The actual model reduction step is formalized and illustrated. This method has been implemented within the CMU version of the SMV model checking tool and validated on a large industrial design.

关键词： Input variables Computational modeling Discrete event simulation Laboratories Conferences System-on-a-chip Real time systems Automata Boolean functions Law

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