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CPDE: A Methodology for the Transparent Distribution of Centralized Smart Grid Programs

IEEE TRANSACTIONS ON parallel AND distributed systems 2021年第2期32卷 342-354页

作者： Nguyen, Thi Thanh Quynh Bobineau, Christophe Debusschere, Vincent Giap, Quang Huy Hadjsaid, Nouredine Univ Grenoble Alpes CNRS Grenoble INP Inst EngnG2Elab F-38000 Grenoble France Univ Grenoble Alpes CNRS Grenoble INP Inst EngnLIG F-38000 Grenoble France Univ Sci & Technol Univ Danang Fac Elect Engn Danang Vietnam

Control and management in smart grids are facing many challenges such as scalability, heterogeneity and technology innovation. This requires a transformation from the traditional centralised paradigm into a distributed one. In this article, a new distributed programming methodology, called Centralised Programming and distributed Execution (CPDE), is proposed. CPDE relies on (i) the abstraction of the whole system as a distributed database;(ii) the use of the Smartlog declarative and reactive rule based language for expressing data manipulation;and (iii) the automatic Smartlog rule distribution according to data distribution. It thus provides a simple and straightforward mean for distributed programming. A centralised algorithm of fair over-voltage regulation of PV systems is used as a typical smart grids study case to validate the methodology and to compare it with centralized implementations. The experiments are implemented in a real-time simulation platform with a network of Raspberry Pis. In addition to showing its correctnes and ease of use, the performance of the CPDE implementation is studied, as well as its sensitivity to the increasing number of computing units and the data distribution. Results are promising and show the clear benefits of this methodology compared to more classical implementations.

关键词： distributed programming CPDE methodology distributed database declarative language Smartlog smart grid

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real time Crime Data Analysis with Hadoop and MapReduce: A Case Study From Sri Lanka

Real Time Crime Data Analysis with Hadoop and MapReduce: A C...

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International Conference on Information Technology Research (ICITR)

作者： Dhanuka Dayawansa Hamza Nauzad Sithara Kumarasingha Uthpala Isuranga Prasanna S. Haddela Samadhi Rathnayake Faculty of Computing Sri Lanka Institute of Information Technology Malabe Sri Lanka

ISBN: (数字)9798331511425

ISBN: (纸本)9798331511432

Modern law enforcement faces significant challenges in managing and analyzing the exponential growth of crime data, which often includes unstructured, high-volume, and real-time information. Traditional relational database systems struggle to handle these complexities, limiting the ability of agencies to derive actionable insights for proactive measures. This research addresses these challenges by proposing a scalable distributed framework utilizing Hadoop and MapReduce for real-time crime data analysis. The objectives include enabling efficient ETL (Extract, Transform, Load) processes, implementing a robust star schema for structured data storage, and providing actionable insights through an integrated real-time dashboard. The methodology employs a multi-node Hadoop cluster for parallel processing, optimizing data integration and analysis capabilities. Results demonstrate significant improvements in processing speed, fault tolerance, and scalability, validated through the framework's application in Sri Lanka's crime data analysis. Findings reveal enhanced resource allocation, crime pattern identification, and operational efficiency for law enforcement. This research establishes a cost-effective, high-performance solution to modern criminological data challenges, with future potential for predictive analytics and machine learning integration.

关键词： Data analysis Law enforcement Scalability Fault tolerant systems Stars Predictive models parallel processing real-time systems Resource management Predictive analytics

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Pruned distributed and parallel Subarray Beamforming for 3-D Underwater Imaging With Fine-Grid Sparse Arrays

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IEEE JOURNAL OF OCEANIC ENGINEERING 2021年第4期46卷 1356-1371页

作者： Zhao, Dongdong Chen, Peng Hu, Yingtian Liang, Ronghua Wang, Haixia Guo, Xinxin Zhejiang Univ Technol Coll Comp Sci & Technol Hangzhou 310023 Zhejiang Peoples R China Zhejiang Univ Technol Coll Informat Engn Hangzhou 310023 Zhejiang Peoples R China Chinese Acad Sci Inst Deep Sea Sci & Engn Sanya 572000 Hainan Peoples R China

The development of real-time 3-D underwater imaging systems with large planar arrays involves high hardware costs and great computational burden. This study proposes the concept of fine-grid sparse arrays and the pruned distributed and parallel subarray (P-DPS) beamforming algorithm to achieve 3-D narrowband underwater imaging systems with low complexity. Fine-grid sparse arrays refine traditional half-wavelength grids to improve the freedom of the sparse optimization process and reduce the number of active elements. However, grid refinement increases the computational load of conventional fast beamforming algorithms. To solve this problem, a new pruned fast Fourier transform is proposed to eliminate all the redundant operations in the P-DPS beamforming, which is suitable for fine-grid sparse arrays. The computational load of the P-DPS beamforming seldom increases with grid refinement. The validity of the proposed method is verified with a fine-grid sparse planar array designed in the study. The computational load is then analyzed and compared with those of other methods. Results show the notable improvements in array sparsity rate and computational efficiency relative to those in the literature.

关键词： Array signal processing Imaging Planar arrays Indexes Genetic algorithms Hardware Transforms Acoustic imaging digital beamforming fine-grid sparse arrays pruned fast Fourier transform (FFT) real-time 3-D underwater imaging simulated annealing (SA) algorithm

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Balancing Energy Efficiency and Portability: Assessing Domain-Specific Languages in Edge Platforms

Balancing Energy Efficiency and Portability: Assessing Domai...

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International Conference on distributed Computing in Sensor systems (DCOSS)

作者： Youssef Faqir-Rhazoui Luis Costero Carlos García Computer Science Faculty Complutense University of Madrid Spain

ISBN: (数字)9798350369441

ISBN: (纸本)9798350369458

Edge computing stands as a crucial component of the IoT revolution. IoT benefits significantly from reduced latency, enhancing real-time applications, and time-sensitive processes. However, since edge platforms must be energy-efficient while maintaining high performance in real-time environments, exploiting accelerators becomes pivotal to reduce energy consumption while increasing performance. CUDA or HIP languages are widely used to program GPUs; however, they are limited to specific vendor platforms. In contrast, solutions such as SYCL or Kokkos could benefit from their ability to run across parallel *** paper explores the trade-offs of CUDA, SYCL, and Kokkos in three Edge platforms: Jetson AGX Orin, Jetson Orin Nano, and UP Squared Pro 7000 (Intel). The work conducts an analysis of the power modes of each platform and compares CUDA, SYCL, and Kokkos on those *** experimental results revealed that, on average, there is an increased level of energy consumption compared to native solutions. Specifically, Kokkos demonstrated a 25% higher demand, whereas SYCL exhibited an average increase of 11%. These figures underscore the trade-off that programmers face in pursuit of achieving code portability when most performant solutions are non-crucial.

关键词： Energy consumption Graphics processing units real-time systems Energy efficiency Internet of Things distributed computing Hip

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Benefits of Optimistic parallel Discrete Event Simulation for Network-on-Chip Simulation

Benefits of Optimistic Parallel Discrete Event Simulation fo...

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International workshop/Symposium on distributed Simulation and real-time Applications (DS-RT)

作者： Maximilian Bremer Nirmalendu Patra Tan Nguyen Dilip Vasudevan Cy Chan Applied Mathematics and Computational Research Division Lawrence Berkeley National Laboratory Berkeley CA USA

The end of Moore's law has placed a two-fold demand on hardware simulation. Firstly, efficient co-design requires fast simulation of hardware systems in order to vet proposed designs. Secondly, modern simulator platforms need to become increasingly concurrent as well. To address these challenges, we develop an optimistic time warp-based parallelization for the Structural Simulation Toolkit (SST). Our optimistic PDES engine hides synchronization costs by speculatively executing tasks, leading to better compute resource utilization on modern multicore architectures. Given the significant engineering effort to make custom existing hardware models reversible, we also develop a new SST component, called escher. The escher workflow instruments arbitrary SST applications and replays event traces through the different SST parallelizations. This is a useful tool for hardware engineers who want to understand the benefits of optimistic parallelization before undertaking the significant software engineering effort to make their hardware models reversible. We demonstrate this workflow by generating traces for a tiled mesh-NOC architecture and show a 2.1x to 3.7x speed-up using our optimistic SST parallelization versus the current conservative SST parallelization.

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Machine Learning Assisted HPC Workload Trace Generation for Leadership Scale Storage systems 22

Machine Learning Assisted HPC Workload Trace Generation for ...

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31st International Symposium on High-Performance parallel and distributed Computing (HPDC)

作者： Paul, Arnab K. Choi, Jong Youl Karimi, Ahmad Maroof Wang, Feiyi Oak Ridge Natl Lab Oak Ridge TN 37830 USA BITS Pilani K K Birla Goa Campus Zuarinagar Goa India

ISBN: (纸本)9781450391993

Monitoring and analyzing a wide range of I/O activities in an HPC cluster is important in maintaining mission-critical performance in a large-scale, multi-user, parallel storage system. Center-wide I/O traces can provide high-level information and fine-grained activities per application or per user running in the system. Studying such large-scale traces can provide helpful insights into the system. It can be used to develop predictive methods for making predictive decisions, adjusting scheduling policies, or providing decisions for the design of next-generation systems. However, sharing real-world I/O traces to expedite such research efforts leaves a few concerns;i) the cost of sharing the large traces is expensive due to this large size, and ii) privacy concern is an issue. We address such issues by building an end-to-end machine learning (ML) workflow that can generate I/O traces for large-scale HPC applications. We leverage ML based feature selection and generative models for I/O trace generation. The generative models are trained on I/O traces collected by the darshan I/O characterization tool over a period of one year. We present a two-step generation process consisting of two deep-learning models, called the feature generator and the trace generator. The combination of two-step generative models provides robustness by reducing the bias of the model and accounting for the stochastic nature of the I/O traces across different runs of an application. We evaluate the performance of the generative models and show that the two-step model can generate time-series I/O traces with less than 20% root mean square error.

关键词： Darshan Generative Modeling Feature Selection Clustering parallel File System

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Analyzing R/X Stability Regions of parallel Grid-Connected Inverters Using Hardware-in-the-Loop Approach

Analyzing R/X Stability Regions of Parallel Grid-Connected I...

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Annual Siberian Russian workshop on Electron Devices and Materials (EDM)

作者： Ilya O. Veretennikov Ildar N. Idrisov Mumu M. Rahman Stepan P. Vasilev Sergei E. Parsegov Federico M. Ibanez Center for Energy Science and Technology Skolkovo Institute of Science and Technology Moscow Russia

ISBN: (数字)9798350389234

ISBN: (纸本)9798350353051

This paper investigates the critical issue of ensuring stable operation in grid-connected inverters and inverter-based distribution grids, focusing on the influence of variable $R / X$ ratios and parallel connections of inverters on system stability in weak grids. Utilizing the power-hardware-in-the-loop methodology, an experimental setup is designed for authentic assessments of grid-connected inverters under diverse conditions. This setup includes an RTDS real-time simulator, a Ponovo 4-quadrant amplifier, a real 4 kW inverter, and a modeled grid with simulated inverters, connected in parallel with the real inverter. The results include experimentally obtained stability regions considering grid R and L parameters. Notably, findings indicate an expanded stability region with parallel inverters, enabling operation with lower $R / X$ ratios. This research contributes to understanding inverter stability at a distribution level of 0.4 kV. The insights gained are crucial for improving grid-connected inverter performance and streamlining the integration of renewable energy sources, thereby advancing the reliability and sustainability of power systems.

关键词： Renewable energy sources Focusing Power system stability Inverters Stability analysis real-time systems Power system reliability

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A Dynamic distributed Scheduler for Computing on the Edge

A Dynamic Distributed Scheduler for Computing on the Edge

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parallel Computing and distributed systems (PCDS), International Symposium on

作者： Fei Hu Kunal Mehta Shivakant Mishra Mohammad AlMutawa Dept. of Computer Science University of Colorado Dept. of Computer Science Kuwait University

ISBN: (数字)9798350349658

ISBN: (纸本)9798350349665

Edge computing is crucial for IoT applications, especially those needing quick, private data handling. However, these applications are resource-intensive, and edge computing resources are limited compared to cloud capabilities. Efficiently using these limited resources is essential to meet all application demands, including latency, privacy, and cost. Due to the dynamic and hybrid nature of IoT environments, static scheduling systems often falls short in meeting these diverse constraints. This paper describes the design, implementation, and evaluation of a dynamic distributed scheduler for the edge. This scheduler schedules the execution of various computing tasks across all computing resources available at the edge in order to satisfy the diverse constraints of an IoT application. The key characteristic of this scheduler is that it constantly monitors the current state of the IoT infrastructure and dynamically adjusts the scheduling of various computing tasks based on the current environmental context as well as the current computing and network conditions. The scheduler utilizes a predictive profiling method to manage the hybrid and variable nature of edge computing resources and tasks. A prototype of this scheduler has been implemented and the paper demonstrates its practicality via an augmented reality application.

关键词： Schedules Privacy Processor scheduling Prototypes parallel processing Dynamic scheduling real-time systems Internet of Things Resource management Edge computing

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Astrea: Auto-Serverless Analytics Towards Cost-Efficiency and QoS-Awareness

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IEEE TRANSACTIONS ON parallel AND distributed systems 2022年第12期33卷 3833-3849页

作者： Jarachanthan, Jananie Chen, Li Xu, Fei Li, Bo Univ Louisiana Lafayette Sch Comp & Informat Lafayette LA 70504 USA East China Normal Univ Sch Comp Sci & Technol Shanghai 200050 Peoples R China Hong Kong Univ Sci & Technol Dept Comp Sci & Engn Hong Kong Peoples R China

With the ability to simplify the code deployment with one-click upload and lightweight execution, serverless computing has emerged as a promising paradigm with increasing popularity. However, there remain open challenges when adapting data-intensive analytics applications to the serverless context, in which users of serverless analytics encounter the difficulty in coordinating computation across different stages and provisioning resources in a large configuration space. This paper presents our design and implementation of Astrea, which configures and orchestrates serverless analytics jobs in an autonomous manner, while taking into account flexibly-specified user requirements. Astrea relies on the modeling of performance and cost which characterizes the intricate interplay among multi-dimensional factors (e.g., function memory size, degree of parallelism at each stage). We formulate an optimization problem based on user-specific requirements towards performance enhancement or cost reduction, and develop a set of algorithms based on graph theory to obtain the optimal job execution. We deploy Astrea in the AWS Lambda platform and conduct real-world experiments over representative benchmarks, including Big Data analytics and machine learning workloads, at different scales. Extensive results demonstrate that Astrea can achieve the optimal execution decision for serverless data analytics, in comparison with various provisioning and deployment baselines. For example, when compared with three provisioning baselines, Astrea manages to reduce the job completion time by 21% to 69% under a given budget constraint, while saving cost by 20% to 84% without violating performance requirements.

关键词： Costs Serverless computing Data analysis Quality of service Optimization Machine learning parallel processing Cloud computing serverless computing resource provisioning modeling optimization

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A Study on Integrating HRRC Network for Robust CVR Solutions

A Study on Integrating HRRC Network for Robust CVR Solutions

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International Conference on Ubiquitous and Future Networks, ICUFN

作者： Sungsoo Choi Jimyoung Kang Power ICT Research Center Korea Electrotechnology Research Institute (KERI) Sa-dong Ansan S. Korea

ISBN: (数字)9798350385298

ISBN: (纸本)9798350385304

Conservation Voltage Reduction (CVR) technology optimizes distribution grid voltage to reduce power demand and losses, improving power system efficiency and stability. Effective real-time monitoring and control of power system voltage and load need a reliable communication network. Ensuring time-sensitive stability in measuring and sharing extensive data from distributed power resources is crucial, especially in unpredictable electrical environments. This paper proposes a solution in the form of a High Reliable Redundancy Communication (HRRC) network. HRRC aims to enhance the network performance and reliability of CVR technology for future power grid systems. The design and implementation of HRRC involves Ethernet-based High Availability Seamless Redundancy (HSR), parallel Redundancy Protocol (PRP), and Merging Unit (MU), offering robust solutions for CVR.

关键词： Protocols Voltage measurement Power measurement Termination of employment distributed databases Power system stability real-time systems

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