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A Low-Complexity and High-Throughput Hardware Design for Lempel-Ziv 4 Compression Algorithm

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Chen, Tao song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

The Lempel-Ziv (LZ) 4 compression algorithm, widely used in data transmission and storage, faces the challenge of high-speed implementation and increased complexity in the era of big data. Therefore, this paper proposes a single-core parallel architecture for LZ4 algorithm with high throughput and low complexity. Firstly, to enhance throughput, two innovative approaches are introduced from the perspective of parallelism and frequency with an acceptable compression ratio loss: each parallelization window is restricted to performing a single match, bridging the gap between actual and theoretical parallelism;the feedback loop in the circuit is broken by utilizing the spatial correlation between adjacent matches for higher frequency. Secondly, two optimization schemes are employed on resource-consuming modules to achieve low complexity. Multi-port hash tables using Live Value Table (LVT) are improved based on inherent data characteristics, significantly reducing the hardware resource consumption while ensuring excellent scalability on hash table depth and frequency. The match comparison operation is moved ahead, further reducing the logic resources by 64.36%. Finally, our design is implemented on FPGA and ASIC platforms. Experimental results on FPGA demonstrate that the proposed architecture achieves a throughput of 17.39 Gb/s, exhibiting a 2.86x improvement over the state-of-the-art, along with a 6.46x enhancement in area efficiency. Further optimizations including Canonic Signed Digit (CSD) coding and computational reuse on the ASIC platform result in a 45x improvement in area efficiency.

关键词： Hardware Throughput Parallel processing Complexity theory Field programmable gate arrays Compression algorithms Encoding Signal processing algorithms Parallel architectures Logic Lossless data compression LZ4 algorithm FPGA ASIC high throughput low complexity hardware accelerator

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A Low-Complexity Soft-Output Massive MIMO Detector With Near-Optimum Performance

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第12期71卷 5445-5456页

作者： Hu, Jinjie song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

In massive multiple-input multiple-output (MIMO) detection, the likelihood ascent search (LAS) algorithm is well-known for its near-optimum performance and low complexity. It employs gradient descent to enhance the performance of suboptimal MIMO detectors, specifically the minimum mean-square error (MMSE) algorithm. In this paper, we introduce several techniques to improve the MMSE-based LAS (MMSE-LAS) algorithm in terms of both complexity and performance. To reduce complexity, the MMSE is first replaced with the low-complexity optimized coordinate descent (OCD) algorithm at the cost of negligible performance loss. Then, the conventional OCD and LAS algorithms are optimized for better computation reuse. Besides, we derive a new soft-output computation formula for LAS to improve the coded performance. The proposed modulation-based successive gradient descent (MB-SGD) detector outperforms MMSE-LAS and the latest work in terms of either complexity or performance for $64\times 8$ and $128\times 8$ LDPC-coded MIMO systems with multiple modulations from QPSK to 256-QAM. The corresponding architecture for a $128\times 8$ coded MIMO system supporting multiple modulations is implemented on a Xilinx Virtex-7 FPGA and with TSMC 28-nm CMOS technology, exhibiting 74.5% lower latency and 0.24 dB gain compared to OCD on FPGA, and also achieving 14.59 $\times$ energy efficiency and 2.04 $\times$ area efficiency over the state-of-the-art implementation on ASIC.

关键词： Detectors Complexity theory Massive MIMO Vectors Modulation Antennas Hardware modulation-based successive gradient descent coordinate descent likelihood ascend VLSI soft-output detector

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第3期71卷 1429-1442页

作者： Chen, Yangyang Feng, Huiyu song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

The expectation propagation (EP) algorithm is near-optimal in massive multiple-input multiple-output (MIMO) systems but suffers from high computation complexity. Most of the previous works exploit the channel hardening property and introduce iterative matrix inversion algorithms to simplify the EP algorithm, but the performance degrades dramatically in non-ideal channels. In this paper, we propose a more universal EP-based detector, which can perform well in both ideal and non-ideal channels. Firstly, two general methods are proposed to effectively improve the detection performance and convergence speed of iterative matrix inversion algorithms under correlated channels. The proposed diagonal preprocessing (DP) method can improve the detection performance by more than 2-dB compared to not using this method;the novel eigenvalue parameter estimation method guarantees the convergence of all the frames. These two methods are applied to the second-order Richardson iteration (SORI) algorithm to derive the DP-SORI algorithm, which converges more than twice as fast as the state-of-the-art design. Secondly, for another important part of EP-based algorithms, namely the calculation of expectation and variance, complicated operations such as exponentiations, divisions, and inversions are all removed by algorithmic optimization. Moreover, based on the proposed approximate EP with DP-SORI (EPA-DP-SORI) algorithm, an efficient hardware design is developed, combining multiple optimization methods such as efficient matrix multiplication architecture design and low-complexity LDL decomposition. In addition to better detection performance compared with the state-of-the-art design, the presented EPA-DP-SORI detector can also deliver 1.27xand 1.57 x higher area and energy efficiency.

关键词： Detectors Approximation algorithms Massive MIMO Detection algorithms Interference Matrix decomposition Iterative algorithms MIMO detection expectation propagation (EP) correlated channels diagonal preprocessing (DP) high throughput hardware implementation

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CSI-Based MIMO Indoor Positioning Using Attention-Aided Deep Learning

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IEEE COMMUNICATIONS LETTERS 2024年第1期28卷 53-57页

作者： Wan, Rongjie Chen, Yuxing song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

Location-based services have become an indispensable component of wireless networks, but high-precision positioning is challenging. With the application of multiple-input multiple-output (MIMO) in 5G, accurate channel state information (CSI) can be obtained and leveraged for high-precision positioning. Solving the MIMO positioning problem by deep learning has demonstrated better accuracy than traditional methods. To further improve the positioning accuracy, we propose a novel deep learning model named ACPNet, which incorporates two types of attention mechanisms and an improved training scheme. Experiment results show that compared to the state-of-the-art work, ACPNet exhibits more than 20% positioning accuracy improvement, and also maintains a relatively low computation complexity.

关键词： Training MIMO communication Deep learning Task analysis Convolution Neural networks Kernel Positioning MIMO CSI deep learning attention mechanism training scheme

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An Area-Efficient Message Passing Detector for Massive MIMO Systems

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第4期69卷 1751-1764页

作者： song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China

Recently, massive multiple-input multiple-output (MIMO) detection schemes based on message passing detection (MPD) have attracted extensive attention due to their good performance-complexity tradeoff. In this paper, to facilitate a high-throughput detector design, we introduce a layered updating schedule and propose an improved layered MPD (ILMPD) algorithm. In the new algorithm, several algorithmic transformations or approximations are derived for lower complexity. For instance, by exploiting the property of quadratic functions, the numbers of multiplications and additions in the constellation matching are both reduced by half;Through reasonable approximations, the multiplication, addition, and sorting operations in the initialization are all removed. Moreover, a lightweight early termination strategy is explored, reducing the number of detection iterations by nearly 20%. Based on the proposed 1LMPD algorithm, an area-efficient architecture is devised, where several optimization methods are proposed for fewer resources and higher clock frequency. Compared with the state-of-the-art design, the presented ILMPD detector can deliver a nearly 3x higher area efficiency. A reconfigurable version of the proposed detector has also been developed, which can well support modulations QPSK to 256-QAM and still exhibits a superior area efficiency.

关键词： Massive MIMO MIMO detection message passing detector channel hardening high throughput low complexity hardware implementation

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Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第3期72卷 1321-1331页

作者： Zhang, Haochen Qiao, Xinyuan Tian, Jing song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Nanjing Univ Sch Integrated Circuits Suzhou 215163 Peoples R China Sun Yat sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

Classic McEliece, with a remarkably stable security level, has been selected as one of the four key-establishment algorithms in the fourth-round evaluation of the post-quantum cryptography (PQC) standardization process of national institute of standards and technology (NIST). However, its memory-intensive and time-consuming key generation poses an obstacle to widespread use. In this paper, we propose a fast hardware implementation of the key generation incorporating several architectural optimizations. For the Gaussian elimination, we optimize the scheduling of computing resources and the memory access process and present a high-performance and flexible systemizer with multiple low fan-out systolic arrays. Besides, an algorithmic-level parallelized design for entry generation and Gaussian elimination is proposed to reduce the redundant computation time. A compact entry generator with a multi-level feedback mechanism and a 2-D high-speed FFT module facilitates continuous streaming the generated entries into the *** implementation results show that our designs for the key generation improve time-area efficiency by 11.9% to 43.2% compared to the state-of-the-arts. Moreover, compared to the hardware implementations for the key generation of the other two quasi-cyclic code-based PQC algorithms, ours for Classic McEliece based on the random code achieves close to or better results in several metrics.

关键词： Hardware Public key Computer architecture Generators Systolic arrays Codes Optimization Polynomials Electronic mail Systematics PQC code-based cryptography classic McEliece FPGA hardware implementation Gauss elimination

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A Novel Low-Complexity Massive MIMO Detector with Near-Optimum Performance

A Novel Low-Complexity Massive MIMO Detector with Near-Optim...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Hu, Jinjie song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen Peoples R China

ISBN: (纸本)9798350330991;9798350331004

In massive multiple-input multiple-output (MIMO) detection, likelihood ascent search (LAS) is well-known for its near-optimum performance with low complexity. It employs gradient descent to enhance the performance of suboptimal MIMO detectors, specifically minimum mean-square error (MMSE). In this paper, we introduce several new techniques to improve the MMSE-based LAS in terms of either complexity or performance. The MMSE is first replaced with optimized coordinate descent algorithm (OCD), which performs near MMSE with lower complexity. Then, the conventional OCD and LAS are reformulated and approximated to better reuse the computation for gradient descent, which is required in both algorithms. Besides, we also optimize the search strategy of LAS, leading to the improvement in both complexity and performance. The proposed detector, modulation-based successive gradient descent (MB-SGD) algorithm, outperforms MMSE-LAS and the latest low complexity near-optimum detector in terms of either complexity or performance for 64x8 and 128x8 MIMO systems under 256-QAM. The corresponding architecture for a 128x8 256-QAM MIMO system has 75.8% lower latency, 2.02 x higher area efficiency, and 03 dB gain when implemented on a Xilinx Virtex-7 FPGA compared to OCD's.

关键词： Massive MIMO modulation-based successive gradient descent coordinate descent likelihood ascent search FPGA design

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A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm 37

A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Comp...

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2024 International Workshop on Signal Processing Systems

作者： Chen, Tao song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen Peoples R China

ISBN: (纸本)9798350373769;9798350373752

This paper delves into recent hardware implementations of the Lempel-Ziv 4 (LZ4) algorithm, highlighting two key factors that limit the throughput of single-kernel compressors. Firstly, the actual parallelism exhibited in single-kernel designs falls short of the theoretical potential. Secondly, the clock frequency is constrained due to the presence of the feedback loops. To tackle these challenges, we propose a novel scheme that restricts each parallelization window to a single match, thus elevating the level of actual parallelism. Furthermore, by restricting the maximum match length, we eliminate the feedback loops within the architecture, enabling a significant boost in throughput. Finally, we present a high-speed hardware architecture. The implementation results demonstrate that the proposed architecture achieves a throughput of up to 16.10 Gb/s, exhibiting a 2.648x improvement over the start-of-the-art. The new design only results in an acceptable compression ratio reduction ranging from 4.93% to 11.68% with various numbers of hash table entries, compared to the LZ4 compression ratio achieved by official software implementations disclosed on GitHub.

关键词： LZ4 lossless compression FPGA high through-put hardware accelerator

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A Low-Area and Low-Power Architecture for Soft-Assisted Product Decoder 5

A Low-Area and Low-Power Architecture for Soft-Assisted Prod...

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5th Information Communication Technologies Conference (ICTC)

作者： Li, Chen song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Peoples R China Sun Yat Sen Univ Shenzhen Peoples R China

ISBN: (纸本)9798350373530;9798350373523

Product code has been proven as an efficient choice for achieving high net coding gain (NCG) at extremely low bit error rates (BER) in fiber communication systems. Compared to the hard-decision product decoders, it has been demonstrated that decoders based on soft-assisted decoding algorithms can achieve excellent decoding performance with only a slight increase in area. However, existing decoders tend to have high power dissipation and large component decoder area due to the fully-parallel architecture. Therefore, further efforts are needed to achieve efficient hardware implementation. In this paper, a low-area and low-power product decoder based on Improved Soft-Assisted Iterative Bounded Distance Decoding algorithm (ISA-iBDD) algorithm is presented. The ASIC synthesis results show that the proposed design leads to an 8.5 x improvement in area efficiency (AE) and a reduction of 62% in energy dissipation compared with the state-of-the-art design.

关键词： Product code BDD algorithm soft-assisted decoding low-power design hardware implementation

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Dual-Bit-Wise Stochastic Decoding for Polar Codes

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2023年 71卷 512-524页

作者： song, suwen Liu, Lu Wang, Zhongfeng Xu, Juyan Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China China Elect Technol Grp Corp CETC Res Inst 58 Wuxi 214061 Peoples R China

codes, being the first class of codes with provable capacity-achieving property, have aroused extensive attention. The belief propagation (BP) algorithm, which is one of the popular decoding approaches for polar codes, possesses inherent high parallelism but also high computational complexity. With low complexity and high fault tolerance, stochastic computing has been well studied and applied to BP decoding for polar codes. However, existing stochastic BP decoders suffer from high decoding latency. In this paper, firstly, a novel dual-bit-wise iterative message update method is proposed for stochastic BP, reducing the decoding latency by more than half. Based on the dual-bit-wise decoding, more special nodes in the factor graph are investigated and then fully exploited to pursue lower decoding complexity than prior arts. Moreover, a well-optimized architecture is developed for the proposed stochastic decoder, where the random number generator (RNG), tracking forecast memory (TFM), and hard decision unit are intelligently designed for reduced hardware cost. Experimental results demonstrate that the presented decoder can exhibit 61.7% lower decoding latency than the state-of-the-art works. Besides, the throughput and hardware efficiency can be improved by nearly 2.8x and 2.7x, respectively.

关键词： Decoding Iterative decoding Polar codes Complexity theory Hardware Throughput Encoding Stochastic computing polar codes belief propagation low latency high throughput low complexity hardware implementation

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