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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Zhang, Qinyuan song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing Peoples R China

ISBN: (纸本)9781665450737

As a type of low-complexity decoding algorithm for low-density parity-check (LDPC) codes, the single-minimum min-sum (smMS) algorithm avoids finding the second minimum, while estimates it by adding a fixed value to the minimum instead. However, the inaccurate estimation of the sub-minimum results in obvious performance degradation. In this work, we propose an improved smMS algorithm, which adds a dynamic value to the minimum based on a special variable that can be easily computed and largely represents the convergence degree of iterative decoding. This new algorithm is thus called dynamic smMS (dsmMS) algorithm. In comparison to the standard normalized min-sum (NMS) algorithm, the performance gap for LDPC code (672,588) is narrowed from 0.55 dB of the smMS to 0.12 dB of the dsmMS. We also present a partially parallel decoding architecture for the dsmMS algorithm, and implement it under 55nm CMOS technology with an area of 0.21 mm(2). Furthermore, compared with the traditional NMS decoder, the proposed design can reduce the area of the total decoder by 22%.

关键词： Low-density parity-check (LDPC) codes lowcomplexity single-minimum min-sum (smMS) algorithm VLSI implementation

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A Low-Latency and Area-Efficient ORBGRAND Decoder for Polar Codes 4

A Low-Latency and Area-Efficient ORBGRAND Decoder for Polar ...

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4th Information Communication Technologies Conference, ICTC 2023

作者： Xiao, Jiayu Zhou, Yangcan song, suwen Wang, Zhongfeng Nanjing University School of Electronic Science and Engineering Nanjing China

ISBN: (纸本)9781665462587

The ultra-reliable low-latency communication (URLLC), one of the three main scenarios in the fifth-generation (5G) mobile communication system, is promising to be used in various emerging applications with stringent latency and performance requirements. Recently, the guessing random additive noise decoding (GRAND) is proposed, which can perform well for the URLLC due to its excellent error-correction performance with short code length. Compared to other variants of the GRAND, the ordered reliability bits GRAND (ORBGRAND) can provide a good trade-off between error-correction performance and hardware overhead. In this work, the ORBGRAND with a reduced schedule for polar codes is implemented for the first time, which utilizes the special structure of the parity-check matrix of polar codes to reduce the decoding latency while keeping the error-correction performance unaltered. Besides, the sorter employed in the ORBGRAND decoder is well optimized to reduce the area occupation. At a target frame error rate of 10-5 when using a (128, 105) 5G polar code, the average decoding latency of the proposed decoder is only 2.46 ns. Moreover, compared to the state-of-the-art ORBGRAND decoder, the proposed decoder can achieve 15% higher decoding throughput and 71% higher area efficiency without any error-correction performance loss. © 2023 IEEE.

关键词： Additive noise

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An Efficient Hardware Design for Fast Implementation of HQC 36

An Efficient Hardware Design for Fast Implementation of HQC

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36th IEEE International System-on-Chip Conference (SOCC)

作者： Li, Chen song, suwen Tian, Jing Wang, Zhongfeng Koc, Cetin Kaya Nanjing Univ Sch Elect Sci & Engn Nanjing Peoples R China Univ Calif Santa Barbara Santa Barbara CA USA

ISBN: (纸本)9798350300116

Hamming Quasi-Cyclic (HQC), as a code-based Key Encapsulation Mechanism (KEM) algorithm, has been selected as one of the three code-based candidates in the fourth round of standardizing post-quantum cryptographic primitives. Efforts are needed for the efficient hardware implementation for HQC. However, in existing hardware designs for HQC, they cost too many clock cycles in the polynomial multiplication module and do not pay enough attention to the decoders used in the decryption. Therefore, this paper presents an improved hardware design for HQC. Through applying a low-latency polynomial multiplication design, every stage of our design saves amounts of clock cycles. Moreover, an efficient Reed-Solomon (RS) decoder based on the enhanced Parallel Inversionless Berlekamp-Massey (ePIBM) algorithm and a Reed-Muller (RM) decoder based on the Fast Hadamard Transform (FHT) algorithm are introduced to reduce the overhead in the decryption. A complete architecture is finally implemented on the Xilinx Artix 7 FPGA (xc7a200t-3). Experimental results show that the proposed design for the HQC-128 requires 25% less area-delay product (ADP) than the latest one in decryption. Furthermore, the proposed design can perform key generation in 0.11ms, encapsulation in 0.22ms, and decapsulation in 0.38 ms, which significantly outperforms the state-of-the-art design.

关键词： Post-quantum cryptography Hamming quasi-cyclic Reed-Solomon decoder Reed-Muller decoder hardware implementation

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An Improved Method for Performance Analysis of Generalized Integrated Interleaved Codes

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IEEE COMMUNICATIONS LETTERS 2021年第10期25卷 3166-3169页

作者： Cui, Hangxuan song, suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210008 Peoples R China

Generalized integrated interleaved (GII) codes show great potential in communication and distributed storage systems for their good error-correction capability and locality. To design GII codes with optimal code parameters, an accurate theoretical performance analysis method is essential, which also benefits the study of decoding behavior. However, the current performance analysis method does not fit simulation results very well and can only provide frame-error-rate (FER) evaluation. This letter presents an improved theoretical performance analysis method, including both bit-error-rate (BER) and FER estimations, which fit simulation results very closely. More importantly, the proposed method could predict the failure probability of each decoding round, thus facilitating a better understanding of decoding behavior. To simplify the analysis, an approximation performance evaluation method is also introduced by relaxing the constrained conditions, which still exhibits similar accuracy.

关键词： Decoding Performance analysis Simulation Iterative decoding Estimation Encoding Software Generalized integrated interleaved (GII) codes locally recoverable codes (LRC) nested decoding theoretical performance analysis

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A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm

arXiv

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arXiv 2024年

作者： Chen, Tao song, suwen Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China School of Integrated Circuits Sun Yat-sen University Shenzhen China

This paper delves into recent hardware implementations of the Lempel-Ziv 4 (LZ4) algorithm, highlighting two key factors that limit the throughput of single-kernel compressors. Firstly, the actual parallelism exhibited in single-kernel designs falls short of the theoretical potential. Secondly, the clock frequency is constrained due to the presence of the feedback loops. To tackle these challenges, we propose a novel scheme that restricts each parallelization window to a single match, thus elevating the level of actual parallelism. Furthermore, by restricting the maximum match length, we eliminate the feedback loops within the architecture, enabling a significant boost in throughput. Finally, we present a high-speed hardware architecture. The implementation results demonstrate that the proposed architecture achieves a throughput of up to 16.10 Gb/s, exhibiting a 2.648× improvement over the start-of-the-art. The new design only results in an acceptable compression ratio reduction ranging from 4.93% to 11.68% with various numbers of hash table entries, compared to the LZ4 compression ratio achieved by official software implementations disclosed on GitHub. Copyright © 2024, The Authors. All rights reserved.

关键词： Compression ratio (machinery)

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A Novel Low-Complexity Massive MIMO Detector with Near-Optimum Performance

A Novel Low-Complexity Massive MIMO Detector with Near-Optim...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Jinjie Hu suwen song Zhongfeng Wang School of Electronic Science and Engineering Nanjing University Nanjing China School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

In massive multiple-input multiple-output (MIMO) detection, likelihood ascent search (LAS) is well-known for its near-optimum performance with low complexity. It employs gradient descent to enhance the performance of suboptimal MIMO detectors, specifically minimum mean-square error (MMSE). In this paper, we introduce several new techniques to improve the MMSE-based LAS in terms of either complexity or performance. The MMSE is first replaced with optimized coordinate descent algorithm (OCD), which performs near MMSE with lower complexity. Then, the conventional OCD and LAS are reformulated and approximated to better reuse the computation for gradient descent, which is required in both algorithms. Besides, we also optimize the search strategy of LAS, leading to the improvement in both complexity and performance. The proposed detector, modulation-based successive gradient descent (MB-SGD) algorithm, outperforms MMSE-LAS and the latest low-complexity near-optimum detector in terms of either complexity or performance for 64×8 and 128×8 MIMO systems under 256-QAM. The corresponding architecture for a 128 × 8 256-QAM MIMO system has 75.8% lower latency, 2.02 × higher area efficiency, and 0.3 dB gain when implemented on a ×Xilinx Virtex-7 FPGA compared to OCD’s.

关键词： Circuits and systems Detectors Mean square error methods Massive MIMO Computer architecture Approximation algorithms Search problems

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A Low-Area and Low-Power Architecture for Soft-Assisted Product Decoder

A Low-Area and Low-Power Architecture for Soft-Assisted Prod...

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Information Communication Technologies Conference (ICTC)

作者： Chen Li suwen song Zhongfeng Wang School of Electronic Science and Engineering Nanjing University Nanjing China Sun Yat-sen University Shenzhen China

ISBN: (数字)9798350373523

ISBN: (纸本)9798350373530

Product code has been proven as an efficient choice for achieving high net coding gain (NCG) at extremely low bit error rates (BER) in fiber communication systems. Compared to the hard-decision product decoders, it has been demonstrated that decoders based on soft-assisted decoding algorithms can achieve excellent decoding performance with only a slight increase in area. However, existing decoders tend to have high power dissipation and large component decoder area due to the fully-parallel architecture. Therefore, further efforts are needed to achieve efficient hardware implementation. In this paper, a low-area and low-power product decoder based on Improved Soft-Assisted Iterative Bounded Distance Decoding algorithm (ISA-iBDD) algorithm is presented. The ASIC synthesis results show that the proposed design leads to an 8.5× improvement in area efficiency (AE) and a reduction of 62% in energy dissipation compared with the state-of-the-art design.

关键词： Product codes Energy dissipation Bit error rate Optical fiber communication Iterative algorithms Hardware Encoding

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A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm

A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Comp...

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IEEE Workshop on Signal Processing Systems (SIPS)

作者： Tao Chen suwen song Zhongfeng Wang School of Electronic Science and Engineering Nanjing University Nanjing China School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (数字)9798350373752

ISBN: (纸本)9798350373769

关键词： Feedback loop Computer architecture Parallel processing Signal processing Throughput Software Parallel architectures Compression algorithms Hardware acceleration Software development management

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An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes

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IEEE COMMUNICATIONS LETTERS 2021年第4期25卷 1153-1157页

作者： song, suwen Tian, Jing Lin, Jun Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China

When non-binary low-density parity-check (NB-LDPC) codes with low column weights are adopted, the iterative reliability-based majority-logic decoding (IRB-MLGD) algorithms suffer from severe performance degradation compared to message passing algorithms. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a perturbation-injected (P)-IISRB algorithm, where a regular perturbation is introduced to alleviate the periodic point problem that is the main reason for IISRB decoding failure. Compared with the conventional IISRB, the new algorithm significantly improves the decoding performance, lowering the error-floor by at least two orders of magnitude for the example code. Besides, instead of traditionally pre-computing and storing all the q-ary channel reliability measures, a real-time computing method is presented, which reduces the memory cost from O(q) to O(log(2) q).

关键词： Reliability Iterative decoding Perturbation methods Decoding Real-time systems Memory management Computational complexity Error-correction codes non-binary LDPC codes reliability-based decoding majority-logic decoding perturbation

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Sign Aided Adaptive Noisy Gradient Descent Bit-Flipping Algorithm for LDPC Codes 8

Sign Aided Adaptive Noisy Gradient Descent Bit-Flipping Algo...

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8th IEEE International Conference on Computer and Communications, ICCC 2022

作者： Deng, Keyue Chen, Yuxing song, suwen Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China

ISBN: (纸本)9781665450515

The adjustment factor aided noisy gradient descent bit-flipping (ANGDBF) offers a significant improvement in error correction capability compared with other gradient descent bit-flipping (GDBF) variants. However, there still exists a considerable performance gap between the ANGDBF algorithm and the belief propagation (BP) algorithm. This paper presents a sign aided adaptive noisy GDBF (SANGDBF) algorithm, in which the mean of noise perturbation shows an adaptive property, facilitating the decoding process to escape from the local maxima more effectively. Moreover, the sign of the correlation term is fully utilized to improve the reliability of the inversion function. Simulation results show that the SANGDBF algorithm can achieve about 0.5 dB coding gain compared with the ANGDBF algorithm with limited hardware overhead. © 2022 IEEE.

关键词： Iterative decoding

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