The architecture of carry chains in Field-Programmable Gate Array(FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the archi...
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The architecture of carry chains in Field-Programmable Gate Array(FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8 N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter(TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy.
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