This paper presents a hardware-optimized variant of the well-known Gaussian elimination and its IEEE-754 single-precision FPGA implementation with highly efficient design, which is worked as an Application function un...
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This paper presents a hardware-optimized variant of the well-known Gaussian elimination and its IEEE-754 single-precision FPGA implementation with highly efficient design, which is worked as an Application function unit (AFU) in a loosely-coupled reconflgurable computing prototype system. In this design, pipelined floating-point operators are employed supported by opensource FPLibrary. The design is mainly composed of uniformly distributed entries, yielding a standalone worst case runtime of O(n2) opposed to O(n 3) of the software replication. The results indicate that 15 times-speedup is achieved comparing to the software run by a 2.6GHz Pentium4 CPU with IGB main memory. To evaluate the hardware, a simple model of reconfigurable system has also been proposed using a Xilinx ML555 board which connects and communicates with a desktop computer via the PCIe port. DMA access method is used for data block transport between host and AFU. To the best of authors' knowledge, there is no efficient floating-point FPGA for solving Linear systems of equations (LSEs) in the previous work.
Y2000-62028-613 0100361BATEL:先进电信用的球形栅阵列技术.第1部分=BATEL:ball grid array technologies for advanced tele-com *** J[会,英]/Kelly.G.& Schols-G./1999 IEEE 49th Electronic Components and Tech-nology Confer...
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Y2000-62028-613 0100361BATEL:先进电信用的球形栅阵列技术.第1部分=BATEL:ball grid array technologies for advanced tele-com *** J[会,英]/Kelly.G.& Schols-G./1999 IEEE 49th Electronic Components and Tech-nology Conference.—613～618(PC)Y2000-62364-65 0100362高级合成(含4篇文章)=Session 5:high level synthesis[会,英]//Proceedings of the Ⅻ Symposium on Integrat-ed Circuits and Systems Design(SBCC199).
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