Networked discrete-event systems consist of physically coupled subsystems that utilise a digital communication network for solving their current tasks. Each subsystem has to be steered from its current state into a si...
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Networked discrete-event systems consist of physically coupled subsystems that utilise a digital communication network for solving their current tasks. Each subsystem has to be steered from its current state into a situation-dependent target state. Due to the physical couplings among the subsystems, certain state transitions have to be executed synchronously with other subsystems to reach the local target states. To satisfy all local tasks, the subsystems have to find a deadlock-free order of the synchronous state transitions by applying global model information. However, in the networked discrete-event system there does not exist any coordinator and the global model information is distributed among the subsystems. Hence, the subsystems have to exchange model information and to compose it online to find the deadlock-free order of synchronous state transitions. This paper proposes an online model composition algorithm based on the A ⁎ -algorithm that determines the necessary local model information to be communicated and composed by the subsystems. The method is demonstrated by an example.
This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high faul...
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This work describes a test generation package developed to utilize the special features of PPL arrays (a structured logic design methodology developed by the VLSI group at the University of Utah) to generate high fault coverage test vectors at a reduced computational cost. The test strategy assumes that one of the scan design techniques is used. A fault oriented test generation algorithm combined with a heuristic test generation algorithm are the essential ingredients of this package. The heuristic algorithm generates an initial set of test vectors which is verified against a predefined list of possible faults. A fault oriented algorithm is then used to generate test vectors that can detect faults not detected by this set. The fault oriented algorithm uses a modified D -algorithm which includes look ahead features and a new seven valued logic to improve the average speed of the test generation process. Fault coverages in the 90% range were obtained using the test vectors generated by this package. Test vectors generated by both algorithms can optionally be stitched into sequences in a way that does not compromise their fault coverage. This reduces the overhead in actual test application time by cutting down the number of the serial scan in/out operations.
Utilization of the logic programming language Prolog in solving CAD/CAM/CAT problems is discussed. It is demonstrated through examples that, with Prolog , solutions are obtained through proper problem definition rathe...
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Utilization of the logic programming language Prolog in solving CAD/CAM/CAT problems is discussed. It is demonstrated through examples that, with Prolog , solutions are obtained through proper problem definition rather than by algorithmic procedures. The examples offered are in the area of test generation for digital circuits. A very simple formulation of the D-algorithm is presented, and it is demonstrated that levelling of the circuit is not necessary. Finally, we suggest other areas of CAD/CAM/CAT that may take advantage of logic programming.
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